• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.10 no.7
• /
• pp.3231-3244
• /
• 2016

As processor design has been transiting from homogeneous multicore processor to heterogeneous multicore processor, traditional Amdahl's law cannot meet the new challenges for asymmetric multicore system. In order to further investigate the impact factors related to the Overhead of Data Preparation (ODP) for Asymmetric multicore systems, we evaluate an asymmetric multicore system built with CPU-GPU by measuring the overheads of memory transfer, computing kernel, cache missing and synchronization. This paper demonstrates that decreasing the overhead of data preparation is a promising approach to improve the whole performance of heterogeneous system.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.14 no.3
• /
• pp.163-169
• /
• 2014

Recently, the importance of multicore processor system is growing rapidly. Multicore processors are classified either as symmetric or asymmetric. Asymmetric multicore processors consist of a high performance complex core and number of low performance simple cores, and are known to be more efficient than symmetric multicore processors. Therefore, performance impact on various configurations of asymmetric multi-core processor needs to be studied. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for different asymmetric quad-core and octa-core processors and compared to the corresponding symmetric ones.

• Journal of KIISE
• /
• v.43 no.9
• /
• pp.1060-1065
• /
• 2016

Recently, there is an emerging need for parallel UHD video processing, and the usage of computing systems that have an asymmetric processor such as ARM big.LITTLE is actively increasing. Thus, a new parallel UHD video processing method that is optimized for the asymmetric multicore systems is needed. This paper proposes a novel HEVC tile partitioning method for parallel processing by analyzing the computational power of asymmetric multicores. The proposed method analyzes (1) the computing power of asymmetric multicores and (2) the regression model of computational complexity per video resolution. Finally, the model (3) determines the optimal HEVC tile resolution for each core and partitions/allocates the tiles to suitable cores. The proposed method minimizes the gap in the decoding time between the fastest CPU core and the slowest CPU core. Experimental results with the 4K UHD official test sequences show average 20% improvement in the decoding speedup on the ARM asymmetric multicore system.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.16 no.1
• /
• pp.233-238
• /
• 2016

Recently, the multi-core processor architecture is widely adopted in the embedded processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multicore processors are known to score higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core embedded processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric embedded dual-core, quad-core, octa-core and hexadeca-core processors and compared with the symmetric ones of similar hardware budget using MiBench benchmarks as input.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2013.11a
• /
• pp.180-183
• /
• 2013

근래의 프로세서는 하나의 다이 위에 여러 개의 코어를 배치한 멀티코어 형태를 띠고 있다. 최근에는 프로세서의 에너지 소비량을 줄이기 위해 비대칭 멀티코어를 활용하여 동일한 성능을 유지하며 소비전력을 낮추는 방법에 대한 연구가 활발히 진행되고 있다. 비대칭 멀티코어의 장점을 최대한 활용하기 위해서는 대칭형 멀티코어와는 달리 실행해야 할 프로세스와 상이한 코어간의 작동 특성을 고려해야 한다. 본 논문에서는 전력 소비 효율 향상을 위해 프로세스 스케줄링 알고리즘에 하이브리드 인공지능 기술인 Adaptive Neuro Fuzzy Inference System (ANFIS)를 적용하여 각 프로세스에 적합한 코어를 찾아 할당하는 방법을 제안한다. 시뮬레이션 결과 제안하는 프로세스 스케줄러는 리눅스의 CFS 대비 평균 35.4% 낮은 Energy Delay Product (EDP)를 보였으며 이를 통해 하이브리드 인공지능을 적용한 프로세스 스케줄링 알고리즘의 유효성을 입증하였다.