• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.113-116
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• 2003

Confluence buffers and single flux quantum (SFQ) switches are essential components in constructing a high speed superconductive Arithmetic Logic Unit (ALU). In this work, we developed a SFQ confluence buffer and an SFQ switch. It is very important to optimize the circuit parameters of a confluence buffer and an SFQ switch to implement them into an ALU. The confluence buffer that we are currently using has a small bias margin of $\pm$11％. By optimizing it with a Josephson circuit simulator, we improved the design of confluence buffer. Our simulation study showed that we improved bias global margin of 10％ more than the existent confluence buffer. In simulations, the minimal bias margin was $\pm$33％. We also designed, fabricated, and tested an SFQ switch operating in a DC mode. The mask layout used to fabricate the SFQ switch was obtained after circuit optimization. The test results of our SFQ switch showed that it operated correctly and had a reasonably wide margin of $\pm$15％.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.123-126
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• 2003

RSFQ (Rapid Single Flux Quantum) circuits are used in many practical applications. RSFQ DFFC (Delay Flip-Flop with complementary outputs) circuits can be used in a RAM, an ALU (Arithmetic Logic Unit), a microprocessor, and many communication devices. A DFFC circuit has one input, one switch input, and two outputs (output l and output 2). DFFC circuit functions in such way that output 1 follows the input and output 2 is the complement of the input when the switch input is "0." However, when there is a switch input "1."the opposite output signals are generated. In this work, we have designed an RSFQ DFFC circuit based on 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology. As circuit design tools, we used Xic, WRspice, and Lmeter After circuit optimization, we could obtain the bias current margins of the DFFC circuit to be above 32％.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.981-984
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• 1993

During the past decade, several specific hardwares for fast fuzzy inference have been developed. Most of them are dedicated to a specific inference method and thus cannot support other inference methods. In this paper, we present a hardware architecture called KAFA(KAist Fuzzy Accelerator) which provides various fuzzy inference methods and fuzzy set operators. The architecture has SIMD structure, which consists of two parts; system control/interface unit(Main Controller) and arithmetic units(FPEs). Using the parallel processing technology, the KAFA has the high performance for fuzzy information processing. The speed of the KAFA holds promise for the development of the new fuzzy application systems.

• Proceedings of the Korea Water Resources Association Conference
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• 2018.05a
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• pp.271-271
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• 2018

그래픽 처리 장치(GPU: Graphic Processing Units)는 그래픽 처리에 특화된 수많은 산술논리연산자 (ALU: Arithmetic Logic Unit)와 이에 관련된 인스트럭션Instruction)으로 인해 중앙 처리 장치(CPU: Central Processing Units) 보다 훨씬 빠른 계산 처리를 수행할 수 있다. 최근에는 FORTRAN에 의해 구현된 많은 수치모형들이 현실적인 모델링 방법의 발달로 인해 더 많은 계산량과 계산시간을 필요로 한다. 이 연구에서는 GPU 상의 범용 계산GPGPU : General-Purpose computing on Graphics Processing Units) 기반 운동파 강우유출모형(Kinematic Wave Rainfall-Runoff Model)이 CUDA(Compute Unified Device Architecture) FORTRAN을 사용하여 구현되었다. CUDA FORTRAN 운동파 강우유출모형의 계산 결과는 검증된 CPU 기반 운동파 강우유출모형의 계산 결과와 비교하여 검증되었으며, 잘 일치함을 보여 주었다. CUDA FORTRAN 운동파 강우유출모형은 CPU 기반 모형에 비해 약 20 배 더 빠른 계산 시간을 보였다. 또한 계산 영역이 커짐에 따라 CPU 버전에 비해 CUDA FORTRAN 버전의 계산 효율이 향상되었다.

• The Pure and Applied Mathematics
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• v.30 no.3
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• pp.337-345
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• 2023

Different versions of the boundary Schwarz lemma for the 𝒩 (𝜌) class are discussed in this study. Also, for the function g(z) = z+b₂z²+b₃z³+... defined in the unit disc D such that g ∈ 𝒩 (𝜌), we estimate a modulus of the angular derivative of g(z) function at the boundary point 1 ∈ 𝜕D with g'(1) = 1 + 𝜎 (1 - 𝜌), where ${\rho}={\frac{1}{n}}{\sum\limits_{i=1}^{n}}g(c_i)={\frac{g^{\prime}(c_1)+g^{\prime}(c_2)+{\ldots}+g^{\prime}(c_n)}{n}}{\in}g^{\prime}(D)$ and 𝜌≠1, 𝜎 > 1 and c₁, c₂, ..., c_n ∈ 𝜕D. That is, we shall give an estimate below |g"(1)| according to the first nonzero Taylor coefficient of about two zeros, namely z = 0 and z ≠ 0. Estimating is made by using the arithmetic average of n different derivatives g'(c₁), g'(c₂), ..., g'(c_n).

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.409-414
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• 1986

To eliminate the requirement of multiplications in nonrecursive filter realization, the use of a delta modulation(DM) has been studied by several researchers. However, the structure of DM filters inevitably contains an intergrator that is cascaded with the arithmetic unit to operate convolution summation. In this paper we porpose a method to determine the coefficients that may be used for implementation of a DM filter without an integrator. Also, we obtain the condition by which one can exclude the response errors due to the elimination of the integrator. By computer simulations it is shown that the performance of the proposed filter is very good, providing that the condition is satisfied.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.8
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• pp.1095-1102
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• 2021

A scalable ECC architecture with high scalability and flexibility between performance and hardware complexity is proposed. For architectural scalability, a modular arithmetic unit based on a one-dimensional array of processing element (PE) that performs finite field operations on 32-bit words in parallel was implemented, and the number of PEs used can be determined in the range of 1 to 8 for circuit synthesis. A scalable algorithms for word-based Montgomery multiplication and Montgomery inversion were adopted. As a result of implementing scalable ECC processor (sECCP) using 180-nm CMOS technology, it was implemented with 100 kGEs and 8.8 kbits of RAM when N_PE=1, and with 203 kGEs and 12.8 kbits of RAM when N_PE=8. The performance of sECCP with N_PE=1 and N_PE=8 was analyzed to be 110 PSMs/sec and 610 PSMs/sec, respectively, on P256R elliptic curve when operating at 100 MHz clock.

• Journal of Korea Water Resources Association
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• v.56 no.7
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• pp.431-438
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• 2023

Many shorelines are facing the beach erosion. Considering the climate change and the increment of coastal population, the erosion problem could be accelerated. To address this issue, developing a sediment transport model for rapidly predicting terrain change is crucial. In this study, a sediment transport model based on GPU parallel arithmetic was introduced, and it was supposed to simulate the terrain change well with a higher computing speed compared to the CPU based model. We also aim to investigate the model performance and the GPU computational efficiency. We applied several dam break cases to verified model, and we found that the simulated results were close to the observed results. The computational efficiency of GPU was defined by comparing operation time of CPU based model, and it showed that the GPU based model were more efficient than the CPU based model.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.31 no.4D
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• pp.595-601
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• 2011

There is currently applied to the unit cost per a distance (KRW/km) for estimating the conceptual cost of civil work on basic planning stage of high speed railroad. This unit cost is an arithmetic average value based on historical data, which could be in big error. It also is difficult to explain the deficiency comparing the estimated cost derived from next basic design stage. This study provides the conceptual estimation model using by the parametric method and regression analysis. Independent variables are the distance and the geological materials (earth, weathered rock, soft-rock, hard-rock), extracting from the actual data to 36 contracts. The deviation between the unit costs estimated using the developed model and the actual cost data is presented in the range from -0.4% to +31%. This range is acceptable compared the typical range "-30% to + 50%". This model will improve the accuracy of existing method and be expected to contribute to effective total cost management and the economic aspects, reduce the financial expenditure.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.4
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• pp.143-150
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• 2013

The School Curriculum amend in 2007 mandates the contents from which students can learn the principles and concepts of computer science. Computer Science is one of the most rapidly changing subjects, and the Informatics textbook should accurately explain the basic principles and concepts based on the latest technology. However, we found that the middle school textbooks in circulation lack accuracy and consistency in describing CPU. This paper attempted to discover the root-cause of the fallacy and suggest timely and appropriate explanation based on the historical and technical analysis. According to our study, it is appropriate to state that CPU is composed of datapath and control unit. The Datapath performs operations on data and holds data temporarily, and it is composed of the hardware components such as memory, register, ALU and adder. The Control unit decides the operation types of datapath elements, main memory and I/O devices. Nevertheless, considering the technological literacy of middle school students, we suggest the terms, 'arithmetic part' and 'control part' instead of datapath and control unit.