• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.344-354
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• 2005

In this paper, we proposed a new lifting architecture for JPEG2000 and implemented to ASIC. We proposed a new cell to execute unit calculation of lifting using the property of lifting which is the repetitious arithmetic with same structure, and then recomposed the whole lifting by expanding it. After the operational sequence of lifting arithmetic was analyzed in detail and the causality was imposed for implementation to hardware, the unit cell was optimized. A new lifting kernel was organized by expanding simply the unit cell, and a lifting processor was implemented for Motion JPEG2000 using it. The implemented lifting kernel can accommodate the tile size of $1024{\times}1024$, and support both lossy compression using the (9,7) filter and lossless compression using (5,3) filter. Also, it has the same output rate as input rate, and can continuously output the wavelet coefficients of 4 types(LL, LH, HL, HH) at the same time. The implemented lifting processor completed a course of ASIC using $0.35{\mu}m$ CMOS library of SAMSUNG. It occupied about 90,000 gates, and stably operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the improved operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the performance can be identified in comparison with the previous researches and commercial IPs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.7C
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• pp.647-657
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• 2005

In this paper, we proposed a new lifting architecture for JPEG2000 and implemented to ASIC. We proposed a new cell to execute unit calculation of lifting using the property of lifting which is the repetitious arithmetic with same structure, and then recomposed the whole lifting by expanding it. After the operational sequence of lifting arithmetic was analyzed in detail and the causality was imposed for implementation to hardware, the unit cell was optimized. A new lifting kernel was organized by expanding simply the unit cell, and a lifting processor was implemented for Motion JPEG2000 using it. The implemented lifting kernel can accommodate the tile size of 1024$\times$1024, and support both lossy compression using the (9,7) filter and lossless compression using (5,3) filter. Also, it has the same output rate as input rate, and can continuously output the wavelet coefficients of 4 types(LL, LH, HL, HH) at the same time. The implemented lifting processor completed a course of ASIC using 0.35$\mu$m CMOS library of SAMSUNG. It occupied about 90,000 gates, and stably operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the improved operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the performance can be identified in comparison with the previous researches and commercial IPs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.21-30
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• 1990

This paper describes a hardware implementation of the interframe monochrome video CODEC using a MC-CVQ(Motion Compensated and Classified Vector Quantization) algorithm. The specifications of this CODEC are (1) the resolution of image is $128{\times}128$ pixels, and (2) the transmission rates are about 10frames/sec at the 64Kbps channel. In order to design the CODEC under these conditions, it is implemented by a multiprocessor system composed of MC unit, CVQ nuit and decoder unit, which are controlled by microprogramming technique. And the 3~stage pipelined ALU(Arithmetic and Logic Unit) is adopted to calculate the minimum error distance in the MC unit and CVQ nuit. The realized system shows that the transmission rates are 6-15 frames/sec according to the relative motion of the video signal.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.3
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• pp.301-306
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• 2008

Drivers are becoming more fatigued and uncomfortable with increase in traffic density, and this condition can lead to slower reaction time. Consequently, they may face the danger of traffic accidents due to their inability to cope with frequent gear shifting. To reduce this risk, some drivers prefer automatic transmission (AT) over manual transmission (MT). The AT offers more superior drivability and less shifting shock than the MT; therefore, the AT market share has been increasing. The AT is controlled by an electronic control unit (ECU), which provides better shifting performance. The transmission control unit (TCU) is a higher-value-added product, so the companies that have advanced technologies end to evade technology transfer. With more cars gradually using the ECU, the TCU is expected to be faster and more efficient for organic communication and arithmetic processing between the control systems than the l6-bit controller. In this paper, the model of an automatic transmission vehicle using MATLAB/Simulink is developed for the Hardware in-the-Loop (HIL) simulation with a 32-bit embedded system, and also the AT control logic for shifting is developed by using MATLAB/Simulink. The developed AT control logic, transformed automatically by real time workshop toolbox, is loaded to a 32-bit embedded system platform based on Freescale's MPC565. With both vehicle model and 32-bit embedded system platform, we make the HIL simulation system and HIL simulation of AT based on real time operating system (RTOS) is performed. According to the simulation results, the developed HIL simulator will be used for the performance test of embedded system for AT with low cost and effort.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.197-212
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• 1990

This paper present a new design concept of a single chip 16-bit data path using the concept of modular design, the whole system is divided into several blocks which can be operated as an independent system itself. Making the internal blocks can act as a subsystem, it is possible to shorten design turn-around time, to be redesigned effectively, and to optimize the system performance. The designed system is data path. The data path is to manipulate 16-bit integer data. It is composed of aritmetic logic unit, register file, barrel shifter and bus circuit. The widths and lengths of gate in the circuit were determined using SPICE2. The results of circuit simulation were in good agreement with expected circuit characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.415-418
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems such as WiMAX and WLAN. The conventional DFU which is based on min-sum decoding algorithm needs conversions between two's complement values and sign-magnitude values, resulting in complex hardware. In this paper, a new design of DFU that is based on sign-magnitude arithmetic is proposed to achieve a simplified circuit and high-speed operation.

• ETRI Journal
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• v.26 no.6
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• pp.513-519
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• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.751-754
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• 2005

In this paper, we designed a vertex shader for mobile devices. Proposed Vertex shader is compatible with the OpenGL ARB & DirectX 8.0 Vertex Shader 1.1 and is organized of modified IEEE-754 24 bits float point SIMD architecture. All float point arithmetic unit process 1 cycle operation with 100Mhz frequency more. We made a vertex shader demo system with Xilinx-Virtex II and get synthesis result that confirm 11M gates size at TSMC 0.13um @ 115MHz.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.389-392
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• 2003

A use of micro processor having H-com functions is gradually increased, and this paper describes the digital servo controller applied to linear pulse motor The TMS320LF2407, made by TI(Texas Instruments Co.), is used as a arithmetic unit in control circuit, designed f3r motor drive and available for the implement of high performance and miniaturization. Also, it can allow the sufficient debugging and downloading into control board for independent operation. A current control in order to carry out a position control is of a digital current control mode, and its implement confirmed the servo control performance of position control.

• Proceedings of the KAIS Fall Conference
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• 2010.11a
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• pp.138-141
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• 2010

본 논문에서는 고안전성 연산제어 장치의 열차제어시스템에 대한 적용성을 평가하여 그 결과를 분석하였다. 고안전성 연산제어 장치의 적용대상으로 열차제어시스템에서 가장 대표적인 지상 ATP 시스템을 선정하였다. 지상 ATP(Automatic Train Protection) 시스템은 다수의 차상 ATP 시스템과 통신하여 각 열차의 위치를 확인하고, 각 열차마다 안전 운행에 필요한 정보이동허가, 제한 속도 등의 열차정보를 전송하는 열차제어시스템의 하나이다. 적용대상 열차제어시스템(지상 ATP)의 고안전성 연산처리 장치의 평가항목으로 입력처리시간, 보팅 성공률, 보팅 용량, 최대 입력처리 개수를 정하였으며, DSV보드 LVDS 전송성능, DSV 메모리 공유 및 보팅성능, 최대 입력처리성능 및 보팅성공률을 시험하여 고안전성 연산처리장치의 적용성을 평가였다.