• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2005년도 추계종합학술대회
• /
• pp.711-714
• /
• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• 한국수학교육학회지시리즈D:수학교육연구
• /
• 제18권1호
• /
• pp.31-40
• /
• 2014

Working with dynamic visual representations can help students-with-computer discover new mathematical ideas. Students translate among multiple representations as a strategy to investigate non-routine problems to explore possible solutions in mathematics classrooms. In this paper, we use the area models as new representations for our secondary students to investigate three problems related to the average speed of a particle. Students show their ideas in the process of investigating arithmetic mean, harmonic mean, and average speed through their created dynamic figures. These figures really utilize dynamic geometry software.

• 대한수학회지
• /
• 제61권1호
• /
• pp.161-181
• /
• 2024

We describe the moduli space of Higgs pairs on an irreducible nodal curve of arithmetic genus one and its geometric structures in terms of the Hitchin map and a flat degeneration of the moduli space of Higgs bundles on an elliptic curve.

• 대한수학회보
• /
• 제56권5호
• /
• pp.1219-1233
• /
• 2019

Let $E{\rightarrow}M$ be an arbitrary vector bundle of rank k over a Riemannian manifold M equipped with a fiber metric and a compatible connection $D^E$. R. Albuquerque constructed a general class of (two-weights) spherically symmetric metrics on E. In this paper, we give a characterization of locally symmetric spherically symmetric metrics on E in the case when $D^E$ is flat. We study also the Einstein property on E proving, among other results, that if $k{\geq}2$ and the base manifold is Einstein with positive constant scalar curvature, then there is a 1-parameter family of Einstein spherically symmetric metrics on E, which are not Ricci-flat.

• 대한수학교육학회지:수학교육학연구
• /
• 제20권3호
• /
• pp.275-292
• /
• 2010

본 연구는 조기대수(Early Algebra)의 연구 동향을 살펴보고, 대수와 관련된 교과의 본질에 대한 탐구를 통하여 조기대수지도에 접근할 수 있는 여러 가지 방법을 논의하였다. 산술과 대수는 형태상 유사하고 대수를 산술의 연장선이라고 보는 관점이 우세하나, 산술과 대수의 근본적인 목적과 기호와 문자의 역할에 있어서 차이가 있다는 인식 또한 제기된다. 또한, 역사적으로 기하가 대수의 출발점이었다는 인식을 할 수 있었다. 본 연구자는 이에 따라 조기대수에 접근할 수 있는 가능성 있는 여러 가지 방향을 도출해 내었다. 조기대수 지도를 위하여 (1) 아동들의 비형식적인 전략을 고려하기 (2) 대수적 관계를 고려한 산술추론하기 (3) 기하적 문제 상황에서 대수추론을 시작하기 (4) 문자와 식의 도구를 제공하기 등을 통하여 조기대수 교육에 접근할 수 있다.

• 대한수학회지
• /
• 제59권6호
• /
• pp.1103-1137
• /
• 2022

Our motivation in this note is to find equal hyperharmonic numbers of different orders. In particular, we deal with the integerness property of the difference of hyperharmonic numbers. Inspired by finiteness results from arithmetic geometry, we see that, under some extra assumption, there are only finitely many pairs of orders for two hyperharmonic numbers of fixed indices to have a certain rational difference. Moreover, using analytic techniques, we get that almost all differences are not integers. On the contrary, we also obtain that there are infinitely many order values where the corresponding differences are integers.

• Smart Structures and Systems
• /
• 제26권3호
• /
• pp.311-318
• /
• 2020

The goal of this study is to analytically and non-stochastically generate structural uncertainty behaviors of isotropic beams and laminated composite plates under plane stress conditions by using an interval finite element method. Uncertainty parameters of structural properties considering resistance and load effect are formulated by interval arithmetic and then linked to the finite element method. Under plane stress state, the isotropic cantilever beam is modeled and the laminated composite plate is cross-ply lay-up [0/90]. Triangular shape with a clamped-free boundary condition is given as geometry. Through uncertainties of both Young's modulus for resistance and applied forces for load effect, the change of structural maximum deflection and maximum von-Mises stress are analyzed. Numerical applications verify the effective generation of structural behavior uncertainties through the non-stochastic approach using interval arithmetic and immediately the feasibility of the present method.

• 대한전자공학회논문지
• /
• 제25권9호
• /
• pp.1115-1124
• /
• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• 한국수학사학회지
• /
• 제22권1호
• /
• pp.41-52
• /
• 2009

1583년 네덜란드의 수학자 시몬 스테빈은 그의 대표작 "십분의 일" (De Thiende)을 출판했다. 이 책에서 스테빈은 모든 수를 동일하게 표현할 수 있는 십진 소수체계를 최초로 제안했다. 이 논문에서는 스테빈이 명시적 목표와 숨겨진 목표를 가지고 새로운 체계를 제안했음을 주장할 것이다. 명시적 목표는 실용 수학자들이 원활하게 사용하기를 바란다는 것이었다. 반면 "십분의 일"에서는 명확히 드러나지 않지만 그의 다른 저술들을 통해 파악되는 숨겨진 목표는 16세기까지 영향을 미치던 아리스토텔레스적인 불연속적인 수와 연속적인 크기의 구분을 철폐하려는 것이었다.

• 대한전자공학회논문지SD
• /
• 제43권2호
• /
• pp.24-33
• /
• 2006

본 논문에서는 휴대용 정보기기 시스템에서 더욱 향상된 실시간 3D 그래픽 가속 능력을 갖는 SoC 구현을 위해 효과적인 3D 그래픽 Geometry 처리 IP 구조를 연구하였다. 이를 기반으로 3D 그래픽 Geometry 처리 과정에 필요한 부동소수점 연산기를 설계하였으며, 내장형 3D 그래픽 국제 표준인 OpenGL-ES를 지원하는 부동소수점 Geometry 프로세서를 설계하였다. 설계된 Geometry 프로세서는 Xilinx-Vertex2 FPGA에서 160k gate의 면적으로 구현되었으며, 80 MHz의 동작주파수 환경에서 실제 3D 그래픽 데이터를 이용하여 Geometry 처리 과정의 성능 측정 실험을 하였다. 실험 결과 80 MHz의 동작주파수에서 초당 1.5M 개의 폴리곤 처리 성능이 확인되었으며, 이는 타 3D 그래픽 가속 프로세서에 비하여 평균 2배 이상의 Geometry 처리 성능이다. 본 지오메트리 프로세서는 Hynix 0.25um CMOS 공정에 의한 측정결과 83.6mW의 소모전력을 나타낸다.