• Title/Summary/Keyword: arithmetic

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The Transition of Error Patterns and Error Rates in Elementary Students' Arithmetic Performance by Going Up Grades and Its Instructional Implication (학년 상승에 따른 초등학생들의 자연수 사칙계산 오답유형 및 오답률 추이와 그에 따른 교수학적 시사점)

  • Kim, Soo-Mi
    • Journal of Elementary Mathematics Education in Korea
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    • v.16 no.1
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    • pp.125-143
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    • 2012
  • This study is designed to see the characteristics of elementary students' arithmetic error patterns and error rates by going up grades and to draw some implications for effective instruction. For this, 580 elementary students of grade 3-6 are tested with the same subtraction, multiplication and division problems. Their errors are analyzed by the frame of arithmetic error types this study sets. As a result of analysis, it turns out that the children's performance in arithmetic get well as their grades go up and the first learning year of any kind of arithmetic procedures has the largest improvement in arithmetic performance. It is concluded that some arithmetic errors need teachers' caution, but we fortunately find that children's errors are not so seriously systematic and sticky that they can be easily corrected by proper intervention. Finally, several instructional strategies for arithmetic procedures are suggested.

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A design of transcendental function arithmetic unit for lighting operation of mobile 3D graphic processor (모바일 3차원 그래픽 프로세서의 조명처리 연산을 위한 초월함수 연산기 구현)

  • Lee, Sang-Hun;Lee, Chan-Ho
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.715-718
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    • 2005
  • Mobile devices is getting to include more functions according to the demand of digital convergence. Applications based on 3D graphic calculation such as 3D games and navigation are one of the functions. 3D graphic calculation requires heavy calculation. Therefore, we need dedicated 3D graphic hardware unit with high performance. 3D graphic calculation needs a lot of complicated floating-point arithmetic operation. However, most of current mobile 3D graphics processors do not have efficient architecture for mobile devices because they are based on those for conventional computer systems. In this paper, we propose arithmetic units for special functions of lighting operation of 3D graphics. Transcendental arithmetic units are designed using approximation of logarithm function. Special function units for lighting operation such as reciprocal, square root, reciprocal of square root, and power can be obtained. The proposed arithmetic unit has lower error rate and smaller silicon area than conventional arithmetic architecture.

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A Construction of the Improved Hardware Arithmetic Operation Unit (개선된 하드웨어 산술연산기 구성)

  • Park, Chun-Myoung
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.1023-1024
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    • 2015
  • This paper propose the method of constructing the improved hardware arithmetic operation unit over galois fields. The proposed the hardware arithmetic operation unit have advantage which is more regularity and extensibility compare with earlier method. Also it is able to apply to any multimedia hardware which is the basic arithmetic operation unit. For the future we will research the processor which is the processing arithmetic and logical operation.

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A Study on Joint Coding System using VF Arithmetic Code and BCH code

  • Sukhee Cho;Park, Jihwan;Ryuji Kohno
    • Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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    • 1998.12a
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    • pp.537-545
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    • 1998
  • This paper is the research about a joint coding system of source and channel coding using VF(Variable-to-fixed length) arithmetic code and BCH code. We propose a VF arithmetic coding method with EDC( Error Detecting Capability) and a joint coding method in that the VF arithmetic coding method with EDC is combined with BCH code. By combining both the VF arithmetic code with EDC and BCH code. the proposed joint coding method corrects a source codeword with t-errors in decoding of BCH code and carries out a improvement of the EDC of a codeword with more than (t+1)-errors in decoding of the VF arithmetic coding with EDC. We examine the performance of the proposed method in terms of compression ratio and EDC.

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A Study on the Understanding and Instructional Methods of Arithmetic Rules for Elementary School Students (초등학생의 연산법칙 이해 수준과 학습 방안 연구)

  • Kim, Pan Soo
    • East Asian mathematical journal
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    • v.38 no.2
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    • pp.257-275
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    • 2022
  • Recently, there are studies the argument that arithmetic rules established by the four fundamental arithmetic operations, in other words, commutative laws, associative laws, distributive laws, should be explicitly described in mathematics textbooks and the curriculum. These rules are currently implicitly presented or omitted from textbooks, but they contain important principles that foster mathematical thinking. This study aims to evaluate the current level of understanding of these computation rules and provide implications for the curriculum and textbook writing. To this end, the correct answer ratio of the five arithmetic rules for 1-4 grades 398 in five elementary schools was investigated and the type of error was analyzed and presented, and the subject to learn these rules and the points to be noted in teaching and learning were also presented. These results will help to clarify the achievement criteria and learning contents of the calculation rules, which were implicitly presented in existing national textbooks, in a new 2022 revised curriculum.

On the Teaching of Mental Arithmetic in Primary Mathematics (초등학교에서의 암산 지도에 관한 논의)

  • 정영옥
    • School Mathematics
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    • v.5 no.2
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    • pp.167-189
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    • 2003
  • Mental arithmetic has recently gained a higher profile in primary school mathematics. The study aims to reflect didactical background of mental arithmetic in number and operations curriculum for primary school mathematics. In order to attain these purposes, the present paper describes the meaning of mathematical literacy and didactical background of mental arithmetic on which have been laid emphasis in relation to mathematical literacy in many countries. Also it shows current suggestions for mental arithmetic instruction in Everyday Mathematics Project in USA, Numeracy Number Project in Great Britain, TAL project based on Realistic Mathematics Education in the Netherlands, and mathe 2000 project in German in order to gain practical ideas for teaching mental arithmetic. Furthermore, it discusses mental strategies of students and didactical models for improving mental arithmetic instruction based on the results of many researches. Under these theoretical foundations, it is analyzed how mental arithmetic is developed in our number and operations curriculum, focused on mental strategies and didactical models. Finally, implications for improving our mental arithmetic instruction are discussed.

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A design of Floating Point Arithmetic Unit for Geometry Operation of Mobile 3D Graphic Processor (모바일 3D 그래픽 프로세서의 지오메트리 연산을 위한 부동 소수점 연산기 구현)

  • Lee, Jee-Myong;Lee, Chan-Ho
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.711-714
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    • 2005
  • We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

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The Hardware Design of CABAC for High Performance H.264 Encoder (고성능 H.264 인코더를 위한 CABAC 하드웨어 설계)

  • Myoung, Je-Jin;Ryoo, Kwang-Ki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.4
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    • pp.771-777
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    • 2012
  • This paper proposes a binary arithmetic encoder of CABAC using a Common Operation Unit including the three modes. The binary arithmetic encoder performing arithmetic encoding and renormalizer can be simply implemented into a hardware architecture since the COU is used regardless of the modes. The proposed binary arithmetic encoder of CABAC includes Context RAM, Context Updater, Common Operation Unit and Bit-Gen. The architecture consists of 4-stage pipeline operating one symbol for each clock cycle. The area of proposed binary arithmetic encoder of CABAC is reduced up to 47%, the performance of proposed binary arithmetic encoder of CABAC is 19% higher than the previous architecture.

An Arithmetic System over Finite Fields

  • Park, Chun-Myoung
    • Journal of information and communication convergence engineering
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    • v.9 no.4
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    • pp.435-440
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    • 2011
  • This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

Arithmetic of finite fields with shifted polynomial basis (변형된 다항식 기저를 이용한 유한체의 연산)

  • 이성재
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.9 no.4
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    • pp.3-10
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    • 1999
  • More concerns are concentrated in finite fields arithmetic as finite fields being applied for Elliptic curve cryptosystem coding theory and etc. Finite fields arithmetic is affected in represen -tation of those. Optimal normal basis is effective in hardware implementation and polynomial field which is effective in the basis conversion with optimal normal basis and show that the arithmetic of finite field with the basis is effective in software implementation.