• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.464-467
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• 2000

In this paper we introduce the network based multi-motors control system using CAN(Controller Area Network) The traditional multi-motors control system has many problems in the view of reliability and economy because of the amount and complexity of wiring noise and maintenance problems etc, These problems are serious especially when the motor controllers are separated widely CAN is generally applied in car networking in order to reduce the complexity of the related wiring harnesses. These traditional CAN application techniques are modified to achieve the real time communication for the multi-motor control system. And also the position synchronization technique is developed and the proposed methods are verified experimentally.

• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.433-442
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• 1995

This paper presents an improved VLSI implementation of a parallel sorter to achieve O(Ν) time complexity. Many fast VLSI sort algorithms have been proposed for sorting N elements in O(log Ν) time. However, most such algorithms proposed have complex network structure without considering data input and output time. They are also very difficult to expand or to use in real applications. After analyzing the chip area and time complexity of several parallel sort algorithms with overlapping data input and output time, the most effective algorithm, the rebound sort algorithm, is implemented in VLSI with some improvements. To achieve O(Ν) time complexity, an improved rebound sorter is able to sort 8 16-bits records on a chip. And it is possible to sort more than 8 records by connecting chips in a chain vertically.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.450-454
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• 2015

In this paper, when points with weights are given in a plane, for an arbitrary constant r, we shall find a square area S such that the sum of weights of points belonging to S is maximized. If the length of the side of S is not given, the problem to find arbitrary rectangular area has been studied. In this paper, we will consider the problem to find a square area with a side of a length r when a constant r is given. We will solve the one dimensional problem in dynamic environment and propose an algorithm with the time complexity of O(nlogn+rn).

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.34-34
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• 2000

One of the basic goals, when considering networks for communication in industrial control applications, is the reduction of complexity of related wiring harnesses. In addition, the networking offers the advantages for industrial control applications, such as ease of cabling, ease of changes in the cabling, ease of adding controller modules, etc. CAN (Controller Area Network) is generally applied in car networking in order to reduce the complexity of the related wiring harnesses. These traditional CAN application techniques are modified to achieve the real time communication for the industrial control applications. In this paper, we propose the method of CAN Identifier assignment for Real-Time network system. This method is can be used to scheduling messages on CAN for Real-Time network system. And also, the real-time network system is developed and the proposed moth(Ids are verified experimentally.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.71-80
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• 1995

The usual approach for desinging a fast multiplier involves finding a way to quickly add up all the partial products, based on parital product recoding scheme and carry-save addition. This paper describes theoretical medels for area and time complexities of Multibit Reconding Paralle Multiplier (MRPM), which is a generalization of the modified Booth recoding scheme. Based on the proposed models, time performance, hardware requirements and area-time efficiency are analyzed in order to determine optimal recoding size for very large scale integration (VLSI) realization of the MRPM. Some simulation results show that the MRPM with large multiplier and multiplicand size has optimal area-time efficiency at the recoding size of 4-bit.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.1
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• pp.11-18
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• 2017

Finite field arithmetic has been extensively used in error correcting codes and cryptography. Low-complexity and high-speed designs for finite field arithmetic are needed to meet the demands of wider bandwidth, better security and higher portability for personal communication device. In particular, cryptosystems in GF($2^m$) usually require computing exponentiation, division, and multiplicative inverse, which are very costly operations. These operations can be performed by computing modular AB multiplications or modular $AB^2$ multiplications. To compute these time-consuming operations, using $AB^2$ multiplications is more efficient than AB multiplications. Thus, there are needs for an efficient $AB^2$ multiplier architecture. In this paper, we propose a low latency Montgomery $AB^2$ multiplier using redundant representation over GF($2^m$). The proposed $AB^2$ multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the proposed $AB^2$ multiplier saves at least 18% area, 50% time, and 59% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as exponentiation, division, and multiplicative inverse.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.5
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• pp.1733-1751
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• 2015

The IEEE 802.15.4 standard not only provides a maximum of seven guaranteed time slots (GTSs) for allocation within a superframe to support time-critical traffic, but also achieves ultralow complexity, cost, and power in low-rate and short-distance wireless personal area networks (WPANs). Real-time wireless body area sensor networks (WBASNs), as a special purpose WPAN, can perfectly use the IEEE 802. 15. 4 standard for its wireless connection. In this paper, we propose an adaptive GTS allocation scheme for real-time WBASN data transmissions with different priorities in consideration of low latency, fairness, and bandwidth utilization. The proposed GTS allocation scheme combines a weight-based priority assignment algorithm with an innovative starvation avoidance scheme. Simulation results show that the proposed method significantly outperforms the existing GTS implementation for the traditional IEEE 802.15.4 in terms of average delay, contention free period bandwidth utilization, and fairness.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1047-1054
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• 2004

In this paper, we present two systolic arrays for computing multiplications in CF(2$\^$m/) generated by an irreducible all one polynomial (AOP). The proposed two systolic mays have parallel-in parallel-out structure. The first systolic multiplier has area complexity of O(㎡) and time complexity of O(1). In other words, the multiplier consists of m(m+1)/2 identical cells and produces multiplication results at a rate of one every 1 clock cycle, after an initial delay of m/2+1 cycles. Compared with the previously proposed related multiplier using AOP, our design has 12 percent reduced hardware complexity and 50 percent reduced computation delay time. The other systolic multiplier, designed for cryptographic applications, has area complexity of O(m) and time complexity of O(m), i.e., it is composed of m+1 identical cells and produces multiplication results at a rate of one every m/2+1 clock cycles. Compared with other linear systolic multipliers, we find that our design has at least 43 percent reduced hardware complexity, 83 percent reduced computation delay time, and has twice higher throughput rate Furthermore, since the proposed two architectures have a high regularity and modularity, they are well suited to VLSI implementations. Therefore, when the proposed architectures are used for GF(2$\^$m/) applications, one can achieve maximum throughput performance with least hardware requirements.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.1
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• pp.1-8
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• 2018

This paper proposes a low complexity super resolution algorithm for frequency modulated continuous wave (FMCW) radar systems for foreign object debris (FOD) detection. FOD radar has a requirement to detect foreign object in small units in a large area. However, The fast Fourier transform (FFT) method, which is most widely used in FMCW radar, has a disadvantage in that it can not distinguish between adjacent targets. Super resolution algorithms have a significantly higher resolution compared with the detection algorithm based on FFT. However, in the case of the large number of samples, the computational complexity of the super resolution algorithms is drastically high and thus super resolution algorithms are difficult to apply to real time systems. In order to overcome this disadvantage of super resolution algorithm, first, the proposed algorithm coarsely obtains the frequency of the beat signal by employing FFT. Instead of using all the samples of the beat signal, the number of samples is adjusted according to the frequency of the beat signal. By doing so, the proposed algorithm significantly reduces the computational complexity of multiple signal classifier (MUSIC) algorithm. Simulation results show that the proposed method achieves accurate location even though it has considerably lower complexity than the conventional super resolution algorithms.