• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.840-841
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• 2012

This paper represent a method of next generation IT fields of embedded systems. we discuss the background why the embedded systems is the importance in the next generation IT fields. Also, we describe the hardware oriented embedded systems, the embedded hardware processor, specified processor. And we discuss the embedded system application fields, i.e. mobile phone application, STB application, telematics fields, home automation, personal digital assistant and so on.

• Journal of Biomedical Engineering Research
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• v.6 no.2
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• pp.13-14
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.1-10
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• 1998

The first thing in designing application-specific instruction set processor is having instruction set closely matching hardware characteristics. This instruction set design problem can be more complicated when cobined with implementation method selection problem of each instruction. Our processor model supports two kinds of instructions-primitive or special instructions. Primitive instructions are implemented using common multifunctional hardware such as ALU. Special instructions require a set of dedicated hardware, which actually functions as a coprocessor to the main processor. In this case, special instructions and primitive instructions can be executed independently. In this paper, we present novel algorithm for genrating special instructions for given application. Parallelism between special instructions and primitive instructions is also considered during the performance estimation stage of generated special instructions.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.1
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• pp.85-91
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• 2014

As RFID is utilized more frequently and diversely in terms of its application areas, the application of mobile RFID technology, which integrates cellular networks and RFID, is highly anticipated. The growth and development of the RFID field has bolstered the development of mobile RFID chips to be embedded in mobile phones. Because mobile RFID chips are embedded in cell phones, limitations such as low power, small form factor, and costliness must be confronted. This study presents the design of a RFID digital baseband processor that is suitable for mobile readers. The RF analog component, which affects the baseband signals, is designed separately, in consideration of the limitations stated above. The function of the baseband processor was verified through simulations and prototyped using FPGA. The power consumption of the chip is 20mW under a 20MHz clock and the chip measures $3mm{\times}3mm$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1152-1157
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• 2002

In this paper, a detailed procedure of development for an AAL2 processor widely used in voice gateway application is introduced. The processor supports CPS and SSCS with voice service and framed mode data service. It provides 4 ATM virtual connections, which include 1020 AAL2 channels. The processor has one UTOPIA Level 1 interface for an ATM cell interface and 4 TDM ports for a voice channel interface. The TDM ports carry PCM/ADPCM voice streams. Most AAL2 processors are implemented as software, or hardware and software, so its latency is large. But this processor has very low latency as to CPS and SSCS because all of them are implemented in hardware. Also, it allows not only loopback and switching of CPS packets, but loopback and switching of TDM channels. The key feature is that the internal structure of the CPS and SSCS in this processor seems like as each software function, so they are called whenever they are required. In addition, they are reusable for another design and are scalable for more channels.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.

• Journal of Korea Foundry Society
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• v.17 no.6
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• pp.552-559
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• 1997

주조방안설계를 위한 pre-processor, main-solver 그리고 post-processor로 구성된 통합 응고해석 시스템을 개발하였다. Pre-processor는 퍼스널 컴퓨터에서 사용되는 상용 CAD 프로그램인 AutoCAD를 사용하였다. Main-solver는 주조과정중의 충진거동을 해석한 유동해석 프로그램과 3차원 열전달 응고해석을 통합하여 냉각수 시스템으로 제어되는 금형 반복주조법에서의 응고양상을 해석할 수 있다. Post-processor는 cavity내의 용탕충진거동, 주형내의 온도분포, 응고시간등을 3차원 그래픽으로 처리할 수 있게 설계하였다. 개발된 시스템의 현장적용 가능성을 검증하기 위하여 대형주강 밀하우징, 자동차휠 주조용품, 밸브블럭등의 시제품의 열유동해석에 적용하였다. 본 연구에서 개발된 CastDesigner는 중소기업형 주조현장에서 PC용 CAD/CAE system 구축을 통한 최적주조방안 설계용 열유동해석 프로그램으로 사료된다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.2
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• pp.84-91
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• 2014

This paper introduces the application of supervisory monitoring system for substation automation based on IEC 61850. The objective of proposed system is detection of such a malfunction or degradation of devices. The supervisory monitoring procedure consists of a two step - topology processor and state estimation. The topology processor using artificial intelligence is a preprocessing step of state estimation. Topology processor identifies the topology structure of switches in substation and detects an error of ON/OFF state data. The state estimation is an algorithm that minimizes an error between optimal estimation values and real values. The proposed system is applied to standard digital substation based on IEC 61850 for performance verification.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.168-176
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• 1996

This paper presetns a 2-D DCT architecture adopting accurac y compensator for reducing the hardware complexity and increasing processing speed in VL\ulcornerSI implementation. In the application fields such as moving pictures experts group (MPEG) and joint photographic experts group (JPEG), 2-D DCT processor must be implemented precisely enough to meet the accuracy specifications of the ITU-T H.261. Almost all of 2-D DCT processors have been implemented using many multiplications and accumulations of matrices and vectors. The number of multiplications and accumulations seriously influence on comlexity and speed of 20D DCT processor. In 2-D DCT with fixed-point calculations, the computation bit width must be sufficiently large for the above accuracy specifications. It makes the reduction of hardware complexity hard. This paper proposes the accuracy compensator which compensates the accuracy of the finite word length calculation. 2-D DCT processor with the proposed accuracy compensator shows fairly reduced hardware complexity and improved processing speed.

• 한국신재생에너지학회:학술대회논문집
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• 2007.11a
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• pp.19-22
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• 2007

In this study, we investigated operating characteristics of natural gas fuel processor for polymer electrolyte membrane fuel cells (PEMFCs). The fuel processor consists of a natural gas reformer, a water-gas shift reactor, a heat-exchanger and a burner, in which the overall integrated volume is exactly(exceptionally) small, namely, about 10L except outer insulation. The producted hydrogen is $1Nm^3/hr$ and the maximum thermal efficiency is ${\sim}76%$(low heating value) at full operating load. A compact and highly efficient $1Nm^3/hr$ class natural gas fuel processor was developed at UNISON is an advantage for application in residential PEMFCs co-generation systems.