• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10A
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• pp.1015-1022
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• 2007

In this paper, dual-band digital codec for UHF(Ultra High Frequency) and MW(Micro Wave) is proposed for an RFID reader system. Most RFID systems have been supported only one protocol. But, There are many protocols of each bandwidth. Especially, UHF bandwidth which is widely used on the globe consists of A,B,C type, and more standards will be established. Recently, Since an interest about mobile RFID system is increasing, the RFID system with more than one protocol will be need. Therefore, this paper suggests a dual-band digital codec with UHF and MW bands for an RFID reader system. Standards used in this system are 18000-6C and 18000-4 standards. The digital codec is synthesize by the Quartus II compiler. Target device is EPC20Q240C8 which is family of CycloneII. Main Clock is 19.2MHz and elements of FPGA which is used for the system is 18,752.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.175-182
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• 2011

In this paper, we implemented a high-performence memory controller which can accommodate processing blocks(multiple masters) in SoC for video signal processing. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Selector, Mster Arbiter, Memory Signal Generator, Command Decoder, and memory Signal Generator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used. Since the designed H/W can be stably operated in 174.28MHz, it satisfies the specification of SDRAM technology.

• Journal of IKEEE
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• v.21 no.4
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• pp.358-367
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• 2017

Advanced Driver Assistance Systems(ADAS), such as Front Collision Warning System (FCWS) are currently being developed. FCWS require high processing speed because it must operate in real time while driving. In addition, a low-power system is required to operate in an automobile embedded system. In this paper, FCWS is implemented in CPU-FPGA architecture in embedded system to enable real-time processing. The lane detection enabled the use of the Inverse Transform Perspective (IPM) and sliding window methods to operate at fast speed. To detect the vehicle, a Convolutional Neural Network (CNN) with high recognition rate and accelerated by parallel processing in FPGA is used. The proposed architecture was verified using Intel FPGA Cyclone V SoC(System on Chip) with ARM-Core A9 which operates in low power and on-board FPGA. The performance of FCWS in HD resolution is 44FPS, which is real time, and energy efficiency is about 3.33 times higher than that of high performance PC enviroment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.439-446
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• 2011

In this paper, we proposed and implemented a dedicated hardware for Huffman coding which is a method of entropy coding to use compressing multimedia data with video coding. The proposed Huffman codec consists Huffman encoder and decoder. The Huffman encoder converts symbols to Huffman codes using look-up table. The Huffman code which has a variable length is packetized to a data format with 32 bits in data packeting block and then sequentially output in unit of a frame. The Huffman decoder converts serial bitstream to original symbols without buffering using FSM(finite state machine) which has a tree structure. The proposed hardware has a flexible operational property to program encoding and decoding hardware, so it can operate various Huffman coding. The implemented hardware was implemented in Cyclone III FPGA of Altera Inc., and it uses 3725 LUTs in the operational frequency of 365MHz

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.371-374
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• 2009

This Paper deal with a design, making a prtotype and test methods of Real-time towed Line Array Sensor Data processing board for fast data communication and long range transmission with SFM(Serial FPDP Module) through Optic-fiber channel. The LAS A,B,C group Data from towed line array sensor which is installed in FFX(Fast Frigate eXperimental) of Korean Navy is packed a previously agreed protocol and transmitted to the Signal processing unit. Consider the limited space of VME 6U size, LAS Data processing board is designed with MPC8265 PowerPC Controller of Freescale for main system control and Altera's CycloneIII FPGA for sensor data packing, self-test simulation data generation, S/W FIFO et cetera. LAS Data processing board have VxWorks, the RTOS(Real Time Operating System) that present many device drivers, peripheral control libraries on board for real-time data processing.

• Journal of IKEEE
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• v.22 no.4
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• pp.886-895
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• 2018

This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.414-418
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• 2016

In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.

• Journal of Korea Water Resources Association
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• v.45 no.12
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• pp.1309-1319
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• 2012

The East Asia (EA) region including China, Taiwan, Japan, and Korea are especially vulnerable to hydrometerological extremes during the boreal summer (June-September). Therefore, this study pursued an exploratory analysis to improve better understanding of the potential impacts of the PJ pattern on WNP Tropical cyclone (TC) activity and TC-affected extremes based on the Korean Nakdong River Basin. The results show that during the positive PJ years, the large-scale atmospheric environments tend more favorable for the TC activity than those in the negative PJ years. KP-influenced TCs during the positive (negative) PJ years are likely to occur more southwestward (northeastward), recurve at more northwestward (northeastward) locations, and indicate increase (decrease) in frequency over Korea and Japan. Consequently, TCs making landfall are more exhibited over the southeastern portions of South Korea during the positive PJ years.

• Wind and Structures
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• v.25 no.1
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• pp.79-100
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• 2017

The use of wind energy resources is developing rapidly in recent decades. There is an increasing number of wind farms in high wind-velocity areas such as the Pacific Rim regions. Wind turbine towers are vulnerable to tropical cyclones and tower failures have been reported in an increasing number in these regions. Existing post-disaster failure case studies were mostly performed through forensic investigations and there are few numerical studies that address the collapse mode simulation of wind turbine towers under strong wind loads. In this paper, the wind-induced failure analysis of a conventional 65 m hub high 1.5-MW wind turbine was carried out by means of nonlinear response time-history analyses in a detailed finite element model of the structure. The wind loading was generated based on the wind field parameters adapted from the cyclone boundary layer flow. The analysis results indicate that this particular tower fails due to the formation of a full-section plastic hinge at locations that are consistent with those reported from field investigations, which suggests the validity of the proposed numerical analysis in the assessment of the performance of wind-farms under cyclonic winds. Furthermore, the numerical simulation allows to distinguish different failure stages before the dynamic collapse occurs in the proposed wind turbine tower, opening the door to future research on the control of these intermediate collapse phases.

• Korean Journal of Ecology and Environment
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• v.34 no.4 s.96
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• pp.342-348
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• 2001

The present work is to introduce the preliminary experimental results for a primary hydrocyclones process in lake sediment thickening. A few cyclones based on the Rietema standard geometry were prepared. The test particles were sediments from a local lake and waste coal fly ash for a reference test. As a result of the chemical analysis, organic contaminants were abundantly found in smaller particles in overflow. Experimental results showed that the physical characteristics of particles, configuration of the cyclone and operating variables including feed solids concentration and volumetric flow rate could affect the separation efficiency. The limiting feeding velocity for the separation and enrichment of particles was 1.5 m/s, higher separation efficiency, in general, was obtained under the high velocity with the small cyclones.