• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.6-14
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• 2011

This paper presents the design of the battery sensor IC for instrumentation of current, voltage using delta-sigma ADC. The proposed circuit consists of programmable gain instrumentation amplifier (PGIA) and second-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a 0.25 ${\mu}m$ CMOS technology. Design circuit show that the modulator achieves 82 dB signal-to-noise ratio (SNR) over a 2 kHz signal bandwidth with an oversampling ratio (OSR) of 256 and differential nonlinearity (DNL) of ${\pm}$ 0.3 LSB, integral nonlinearity (INL) of ${\pm}$ 0.5 LSB. Power consumption is 4.5 mW.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.166-168
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• 2006

An analog front-end circuit for 13.56MHz ISO/IECl4443 type B compatible RFID tags was designed. The designed circuit includes a rectifier and regulator to generate a stable DC voltage from the RF signal, an over-voltage limiter to protect the circuit from high voltages, an ASK demodulator to extract the data transferred from reader to tag, and a load modulator to transfer data from tag to reader. The functionality of the designed circuit has been verified through simulations using 0.25um CMOS process parameters.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.1001-1002
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• 2006

As most of the powerline modems use spread spectrum modulation method which has strong immunity against the narrowband fading, or psk modulation method, the amplitude of the signal contains no useful informations. In this paper, we used class D amplifier to implement the drive circuit of the analog front end, and showed that it has great superiority over other existing drive circuits in rapidly impedance changing power line channel.

• Journal of Biomedical Engineering Research
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• v.7 no.1
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• pp.59-66
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• 1986

A prototype ultrasound sector B-scanner has been developed where the front-end hardware refers to all the necessary circuits for transmitting the ultrasound pulses into the human body and receiving the reflected echo signals from it. The front-end hardware can generally be divided into three parts, i.e., a pulse generator for insonification, a receiver which is responsible for processing of low-level analog signals, and a steering controller for driving the mechanical sector probe whose functions and design concepts are described in this paper. The front-end hardware is implemented which incorporates the following features: improvement of the axial resolution using a circuit which reduces the ring-down time, flexibility of generating time-gain compensation curve, and adoption of a one-chip microcomputer for generating the rate pulses based on the sensor output waveforms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.28-36
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• 2008

This paper describes a low-power CMOS analog front-end block for UHF band RFID tag chips. It satisfies ISO/IEC 18000-6C and includes a memory block for test. For reducing power consumption, it operates with an internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator can more exactly demodulate than conventional demodulator with low current consumption. It is designed using a $0.18{\mu}m$ CMOS technology. Measurement results show that it can operate properly with an input as low as $0.25V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.37-43
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• 1997

In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

• Journal of IKEEE
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• v.15 no.4
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• pp.324-329
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• 2011

In recent years, the performance and functions of portable devices has increased. so it requires more power efficiency and energy density while using the battery for a long time. therefore Battery pack which are made up from several battery cells in series in order to achieve higher operating voltage is being used. when using a Li-ion battery, we need a protection circuit to protect from overcharge, over discharge, high temperature and over current. Also, when using battery pack, we need to Cell voltage balancing circuit that each cell in tune with the balancing. In this paper, the proposed IC is applicable by mobile devices as well as E-bike, hybrid vehicles, electric vehicles, and is expected to contribute to the development of domestic PMIC.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.2217-2224
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• 2014

This paper deals with system development which measures 12 channel ECG using medical analog front end(AFE) and discriminates arrythmia through signal analysis. Recently, occurrences of cardiac arrest have been increased. So the need of system that diagnoses an arrythmia which results in cardiac arrest is increasing. There are some drawbacks of conventional 12 channel ECG system that it occupies bulk and consists of complicated circuit. To improve those, we made up the system composed of medical AFE, algorithm for discriminating arrythmia and DSP for signal processing. This system can be monitored 12 channel ECG waveforms and the discriminant analysis result of arrhythmia through 7" LCD and received the input through touch pannel. In this study, we conducted normal operation test about output signal of ECG simulator(normal/abnormal ECG signal) to verify the implemented system and performance evaluation of the optimization process for applying arrhythmia algorithm to an embedded environment.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.769-772
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• 2005

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

• ETRI Journal
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• v.36 no.3
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• pp.352-360
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• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.