• Title/Summary/Keyword: algorithm for multiplication

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Design of $AB^2 $ Multiplier for Public-key Cryptosystem (공개키 암호 시스템을 위한 $AB^2 $곱셈기 설계)

  • 김현성;유기영
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.2
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    • pp.93-98
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    • 2003
  • This paper presents two new algorithms and their architectures for $AB^2 $ multiplication over $GF(2^m)$.First, a new architecture with a new algorithm is designed based on LFSR (Linear Feedback Shift Register) architecture. Furthermore, modified $AB^2 $ multiplier is derived from the multiplier. The multipliers and the structure use AOP (All One Polynomial) as a modulus, which hat the properties of ail coefficients with 1. Simulation results thews that proposed architecture has lower hardware complexity than previous architectures. They could be. Therefore it is useful for implementing the exponential ion architecture, which is the tore operation In public-key cryptosystems.

Dynamic stiffness approach and differential transformation for free vibration analysis of a moving Reddy-Bickford beam

  • Bozyigit, Baran;Yesilce, Yusuf
    • Structural Engineering and Mechanics
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    • v.58 no.5
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    • pp.847-868
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    • 2016
  • In this study, the free vibration analysis of axially moving beams is investigated according to Reddy-Bickford beam theory (RBT) by using dynamic stiffness method (DSM) and differential transform method (DTM). First of all, the governing differential equations of motion in free vibration are derived by using Hamilton's principle. The nondimensionalised multiplication factors for axial speed and axial tensile force are used to investigate their effects on natural frequencies. The natural frequencies are calculated by solving differential equations using analytical method (ANM). After the ANM solution, the governing equations of motion of axially moving Reddy-Bickford beams are solved by using DTM which is based on Finite Taylor Series. Besides DTM, DSM is used to obtain natural frequencies of moving Reddy-Bickford beams. DSM solution is performed via Wittrick-Williams algorithm. For different boundary conditions, the first three natural frequencies that calculated by using DTM and DSM are tabulated in tables and are compared with the results of ANM where a very good proximity is observed. The first three mode shapes and normalised bending moment diagrams are presented in figures.

Heuristic Algorithm for Selecting Mutually Dependent Qualify Improvement Alternatives of Multi-Stage Manufacturing Process (다단계제조공정의 품질개선을 위한 종속대안선택 근사해법)

  • 조남호
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.11 no.18
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    • pp.7-15
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    • 1988
  • This study is concerned with selecting mutually dependent quality improvement alternatives with resource constraints. These qualify improvement alternatives art different fro the tradition at alternatives which are independent from each other. In other words, selection of any improvement alternative requires other related specific improvement. Also the overall product quality in a multi stage manufacturing process is characterized by a complex multiplication method rather than a simple addition method which dose not allow to solve a linear knapsack problem despite its popularity in the traditional study. This study suggests a non-linear integer programming model for selecting mutually dependent quality improvement alternatives in multi-stage manufacturing process. In order to apply the model to selecting alternatives. This study also suggests a heuristic mode1 based on a dynamic programming model which is more practical than the non-linear integer programming model. The logic of the heuristic model enables 1) to estimate improvement effectiveness values on all improvement alternatives specifically defined for this study. 2) to arrange the effectiveness values in a descending order, and 3) to select the best one among the alternatives based on their forward and backward linkage relationships. This process repeats to selects other best alternatives within the resource constraints. This process is presented in a Computer programming in Appendix A. Alsc a numerical example of model application is presented in Chapter 4.

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A GF(2163) scalar multiplier for elliptic curve cryptography (타원곡선 암호를 위한 GF(2163) 스칼라 곱셈기)

  • Jeong, Sang-Hyeok;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.05a
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    • pp.686-689
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    • 2009
  • This paper describes a scalar multiplier for Elliptic curve cryptography. The scalar multiplier has 163-bits key size which supports the specifications of smart card standard. To reduce the computational complexity of scalar multiplication on finite field $GF(2^{163})$, the Non-Adjacent-Format (NAF) conversion algorithm based on complementary recoding is adopted. The scalar multiplier core synthesized with a $0.35-{\mu}m$ CMOS cell library has 32,768 gates and can operate up to 150-MHz@3.3-V. It can be used in hardware design of Elliptic curve cryptography processor for smart card security.

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Design of a ECC arithmetic engine for Digital Transmission Contents Protection (DTCP) (컨텐츠 보호를 위한 DTCP용 타원곡선 암호(ECC) 연산기의 구현)

  • Kim Eui seek;Jeong Yong jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.3C
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    • pp.176-184
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    • 2005
  • In this paper, we implemented an Elliptic Curve Cryptography(ECC) processor for Digital Transmission Contents Protection (DTCP), which is a standard for protecting various digital contents in the network. Unlikely to other applications, DTCP uses ECC algorithm which is defined over GF(p), where p is a 160-bit prime integer. The core arithmetic operation of ECC is a scalar multiplication, and it involves large amount of very long integer modular multiplications and additions. In this paper, the modular multiplier was designed using the well-known Montgomery algorithm which was implemented with CSA(Carry-save Adder) and 4-level CLA(Carry-lookahead Adder). Our new ECC processor has been synthesized using Samsung 0.18 m CMOS standard cell library, and the maximum operation frequency was estimated 98 MHz, with the size about 65,000 gates. The resulting performance was 29.6 kbps, that is, it took 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption and decryption, and key exchanges in real time environments.

A Efficient Architecture of MBA-based Parallel MAC for High-Speed Digital Signal Processing (고속 디지털 신호처리를 위한 MBA기반 병렬 MAC의 효율적인 구조)

  • 서영호;김동욱
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.7
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    • pp.53-61
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    • 2004
  • In this paper, we proposed a new architecture of MAC(Multiplier-Accumulator) to operate high-speed multiplication-accumulation. We used the MBA(Modified radix-4 Booth Algorithm) which is based on the 1's complement number system, and CSA(Carry Save Adder) for addition of the partial products. During the addition of the partial product, the signed numbers with the 1's complement type after Booth encoding are converted in the 2's complement signed number in the CSA tree. Since 2-bit CLA(Carry Look-ahead Adder) was used in adding the lower bits of the partial product, the input bit width of the final adder and whole delay of the critical path were reduced. The proposed MAC was applied into the DWT(Discrete Wavelet Transform) filtering operation for JPEG2000, and it showed the possibility for the practical application. Finally we identified the improved performance according to the comparison with the previous architecture in the aspect of hardware resource and delay.

An Algorithm for Efficient multiplication of nxn Boolean matrices for D-Class Computation (D-클래스 계산을 위 한 $n{\times}n$ 불리언 행렬의 효율적 곱셈 알고리즘)

  • Han Jae-Il
    • Proceedings of the Korean Information Science Society Conference
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    • 2005.11a
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    • pp.952-954
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    • 2005
  • D-클래스는 $n{\times}n$ 불리언 행렬의 집합에서 특정 관계(relation)에 따딸라 동치(equivalent) 관계에 있는 불리언 행렬의 집합으로 구성된다. D-클래스 계산은 $n{\times}n$ 불리언 행렬의 전체 집합을 대상으로 이 집합에서 조합할 수 있는 모든 두 $n{\times}n$ 불리언 행렬 사이의 곱셈을 기본적으로 요구한다. 그러나 불리언 행렬에 대한 대부분의 연구는 두 개의 불리언 행렬에 대한 효율적인 곱셈에 집중되었으며 모든 $n{\times}n$ 불리언 행렬 사이의 곱셈에 대한 연구는 최근에야 소수가 보이고 있다. 두개의 $n{\times}n$ 불리언 행렬 곱셈에 대해 최적화된 알고리즘은 현재 알려져 있으나, 모든 $n{\times}n$ 불리언 행렬 사이의 곱셈에 대해 제시된 알고리즘은 아직 실행시간이 크게 향상되지 못하고 있으며 많은 개선과 연구가 필요하다. 본 논문은 개별적인 $n{\times}n$ 불리언 행렬 곱셈 대신 하나의 $n{\times}n$ 불리언 행렬과 불리언 행렬 집합과의 곱셈을 다루고 또한 이 곱셈에서 계산되는 모든 $n{\times}n$ 불리언 행렬을 집합으로 표현하는 방법을 통해 D-클래스 계산을 보다 효율적으로 할 수 있는 알고리즘에 대해 논한다.

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A Study on GPGPU Performance Improvement Technique on GCN Architecture Using OpenCL API (GCN 아키텍쳐 상에서의 OpenCL을 이용한 GPGPU 성능향상 기법 연구)

  • Woo, DongHee;Kim, YoonHo
    • The Journal of Society for e-Business Studies
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    • v.23 no.1
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    • pp.37-45
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    • 2018
  • The current system upon which a variety of programs are in operation has continuously expanded its domain from conventional single-core and multi-core system to many-core and heterogeneous system. However, existing researches have focused mostly on parallelizing programs based CUDA framework and rarely on AMD based GCN-GPU optimization. In light of the aforementioned problems, our study focuses on the optimization techniques of the GCN architecture in a GPGPU environment and achieves a performance improvement. Specifically, by using performance techniques we propose, we have reduced more then 30% of the computation time of matrix multiplication and convolution algorithm in GPGPU. Also, we increase the kernel throughput by more then 40%.

RI-RSA system design to increase security between nodes in RFID/USN environments (RFID/USN 환경에서 노드들간의 보안성 증대를 위한 RI-RSA 시스템 설계)

  • Lee, Seon-Keun
    • Journal of the Korea Society of Computer and Information
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    • v.15 no.11
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    • pp.157-162
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    • 2010
  • Due to the IT development, RFID/USN became very familiar means of communication. However, because of increased number, security, and size constraints of nodes, it is insufficient to implement a variety of services. To solve these problems, this paper suggests RI-RSA, which is an appropriate asymmetric cryptographic system for RFID/USN environment. The proposed RI-RSA cryptographic system is easy to implement. To increase the processing speed, RI-RSA was suggested by subdividing the multiplication section into two-dimensional, where bottleneck phenomena occurs, and it was implemented in the hardware chip level. The simulation result verified that it caused 6% of circuit reduction, and for the processing speed, RI-RSA was 30% faster compare to the existing RSA.

Fast Binary Block Inverse Jacket Transform

  • Lee Moon-Ho;Zhang Xiao-Dong;Pokhrel Subash Shree;Choe Chang-Hui;Hwang Gi-Yean
    • Journal of electromagnetic engineering and science
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    • v.6 no.4
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    • pp.244-252
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    • 2006
  • A block Jacket transform and. its block inverse Jacket transformn have recently been reported in the paper 'Fast block inverse Jacket transform'. But the multiplication of the block Jacket transform and the corresponding block inverse Jacket transform is not equal to the identity transform, which does not conform to the mathematical rule. In this paper, new binary block Jacket transforms and the corresponding binary block inverse Jacket transforms of orders $N=2^k,\;3^k\;and\;5^k$ for integer values k are proposed and the mathematical proofs are also presented. With the aid of the Kronecker product of the lower order Jacket matrix and the identity matrix, the fast algorithms for realizing these transforms are obtained. Due to the simple inverse, fast algorithm and prime based $P^k$ order of proposed binary block inverse Jacket transform, it can be applied in communications such as space time block code design, signal processing, LDPC coding and information theory. Application of circular permutation matrix(CPM) binary low density quasi block Jacket matrix is also introduced in this paper which is useful in coding theory.