• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.10
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• pp.76-86
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• 2011

This paper proposes novel algorithm for anti-islanding of grid-connected photovoltaic(PV) inverter. The islanding of PV systems can cause a variety of problems such as deterioration in power quality and electric shock. To prevent islanding, many anti-islanding methods are researched. Typical methods of anti-islanding are active frequency drift(AFD) and active frequency drift positive feedback(AFDPF). However, the AFD has problem that widely exists non diction zone(NDZ). The AFDPF is a method that improves the AFD method and is detected islanding by changing the chopping fraction(cf). However, The AFDPF does not detect when cf is very small and does not satisfy the IEEE Std. 929-2000 when cf is very big. Therefore, this paper proposes novel anti-islanding method that is simple to implement using virtual resister. The anti-islanding method proposed in this paper is compared with conventional method. The validity of this paper is proved using this result.

• Proceedings of the KIEE Conference
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• 2000.11a
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• pp.214-216
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• 2000

This paper presents an comparative study on the effect of STATCOM and UPFC to the power system static analysis. The effect of STATCOM can be analyzed with PSS/E program which is generally used in power system analysis, while UPFC model for static analysis is not provided yet. Thus, UPFC is equivalently represented as a synchronous condenser and load, while the active and reactive power of the specific transmission line and the voltage of the bus is controlled appropriately. This procedure is implemented by IPLAN which is an external macro program of PSS/E. The simulation results show that UPFC is more effective to control the bus voltage than STATCOM, because UPFC can control not only the bus voltage where the parallel inverter is installed but also the active and reactive power flow in the transmission line where the series inverter is installed.

• Journal of Power Electronics
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• v.12 no.2
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• pp.344-356
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• 2012

In recent years, multilevel technology has become an effective and practical solution in the field of moderate and high voltage applications. This paper discusses an APF with a three-level NPC inverter. Obviously, the application of such converter to APFs is hindered by the problem of the voltage unbalance of DC capacitors, which leads to system instability. This paper comprehensively analyzes the theoretical limitations of the neutral-point voltage balancing problem for tracking different harmonic currents utilizing current switching functions from the space vector PWM (SVPWM) point of view. The fluctuation of the neutral point caused by the load currents of certain order harmonic frequency is reported and quantified. Furthermore, this paper presents a close-loop digital control algorithm of the DC voltage for this APF. A PI controller regulates the DC voltage in the outer-loop controller. In the current-loop controller, this paper proposes a simple neutral-point voltage control method. The neutral-point voltage imbalance is restrained by selecting small vectors that will move the neutral-point voltage in the direction opposite the direction of the unbalance. The experiment results illustrate that the performance of the proposed approach is satisfactory.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.1
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• pp.61-69
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• 1998

In this paper, discrete current control of voltage source inverters is proposed. As a current control scheme, the constant switching frequency predictive current control is adopted and implemented with DSP microprocessor system. In particular, the proposed method is for the compensation of the control lagging due to calculation delays in the microprocessor controller. In controlling the current, the inverter output voltage saturation problem is inevitable and usually affects the current control performance. So, the saturation boundary condition of the inverter output voltage and its effects on the current controal performance of the proposed current control scheme are investigated with experiment. Finally, the proposed scheme is applied to the active power filter system and some results are described for validation.

• Proceedings of the KIPE Conference
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• 2019.11a
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• pp.96-97
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• 2019

Pulse Width Modulation (PWM) is a widely adopted technique to drive the motor using the voltage source inverters. Since they generate high frequency Common Mode (CM) Voltage, a high shaft voltage in induction motor is induced which leads to parasitic capacitive currents causing adverse effects such as premature deterioration of ball bearings and high levels of electromagnetic emissions. This paper presents an Active Cancellation Circuit (ACC) which can significantly reduce the CM voltage hence the common mode current in the three phase induction motor drives. In the proposed method the CM voltage is detected by the capacitors and applied to the frame of the motor to cancel the CM voltage hence the CM current. Unlike the conventional methods the proposed method does not insert the transformer in between the inverter and motor, a high power rating three phase transformer is not required and no losses associated with it. In addition the proposed method is applicable to any kind of PWM motor drives regardless of their PWM methods. The effectiveness of the proposed method is proved by the experiments with a three phase induction motor (1.1kW 415V/60Hz) combined with a three phase voltage source inverter modulated by the Space Vector Modulation (SVM).

• Proceedings of the KAIS Fall Conference
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• 2004.06a
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• pp.193-197
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• 2004

The four-leg Voltage Source Converter(VSC) can use the DC link voltage effectively by the 3-D SVPWM method. Hence the DC battery voltage can be reduced by $15\%$ in comparison to that of the conventional line-interactive UPS system. In this paper a novel line interactive Uninterruptible Power Supply(UPS) using the two four-leg VSCs is proposed. One VSC is in parallel with the ac link reactor of the power source side, and the other is in series with the load. The parallel four-leg voltage source inverter controls the three-phase line voltage independently in order to control the line reactor current indirectly. It eliminates the neutral line current and the active ripple power of the source side using the pqr theory so that unity power factor and the sinusoidal source current can be achieved even though both the source and the load voltages have zero sequence components. The series four-leg voltage source inverter compensates the line voltage and allows it to be balanced and harmonic-free. Both of the parallel and series four-leg voltage source inverters always act as independently controllable voltage sources, so that the three-phase output voltage shows a seamless transition to the backup mode. The feasibility of the proposed UPS system has been investigated and verified through computer simulations results.

• Journal of Power Electronics
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• v.15 no.2
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• pp.504-517
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• 2015

This paper presents a novel switching voltage model and an offset-based pulse width modulation (PWM) scheme for multilevel inverters with unbalanced DC sources. The switching voltage model under a DC voltage imbalance will be formulated in general form for multilevel neutral-point-clamped topologies. Analysis of the reference switching voltages from active and non-active switching voltage components in abc coordinates can enable voltage implementation for an unbalanced DC-source condition. Offset voltage is introduced as an indispensable variable in the switching voltage model for multilevel voltage-source inverters. The PWM performance is controlled through the design of two offset components in a subsequence. One main offset may refer to the common mode voltage, and the other offset restricts its effect on the quality of PWM control in related DC levels. The PWM quality can be improved as the switching loss is reduced in a discontinuous PWM mode by setting the local offset, which is related to the load currents. The validity of the proposed algorithm is verified by experimental results.

• Journal of Power Electronics
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• v.19 no.2
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• pp.509-518
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• 2019

A novel islanding detection method is proposed in this paper. It is based on a frequency drooping PLL, which was presented in a previous work. The cause of errors in the non-detection zone (NDZ) of conventional frequency disturbance islanding detection methods (IDM) is analyzed. A frequency drooping phase-locked-loop (FD-PLL) is introduced into a single-phase grid-connected inverter (SPGCI), which can guarantee that grid current is in phase with the grid voltage. A novel FD-PLL IDM is proposed by improving this PLL. In order to verify the performance of the proposed FD-PLL IDM, a full performance comparison between the proposed IDM and typical existing active frequency drift IDMs is carried out, which includes both dynamic performance and steady performance. With the same NDZ, the total harmonic distortion of the grid-current in the dynamic process and steady state is analyzed. The proposed FD-PLL IDM, regardless of the dynamic or steady process, has the best power quality. Experimental and simulation results verify that the proposed FD-PLL IDM has excellent performance.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.5
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• pp.477-484
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• 2013

This paper proposes a novel switching method of active clamp snubber for efficiency improvement of PV module integrated converter(MIC) system. Recently, MIC solar system is researched about the efficiency and safety. PV MIC system is used active clamp method of snubber circuit for the price and reliability of the system. But active clamp snubber circuit has the disadvantage that system efficiency is decreased for switch operating time because of heat loss of resonant between snubber capacitor and leakage inductance. To solve this problem, this paper proposes a novel switching method of the active clamp. The proposed method is a technique to reduce power consumption by reducing the resonance of the snubber switch operation time and through simulations and experiments proved the validity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.5
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• pp.922-930
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• 2009

An optimized PWM switching strategy for an induction motor voltage control is developed and demonstrated. Space vector modulation in voltage source inverter offers improved DC-bus utilization and reduced commutation losses and has been therefor recognized the preferred PWM method especially in case of digital implementation. An optimized PWM switching strategy for an induction motor voltage control consists of switching between the two active and one zero voltage vector by using the proposed optimal PWM algorithm. The preferred switching sequence is defined as a function of the modulation index and period of a carrier wave. The sequence is selected by using the inverter switching losses and the current ripple as the criteria. For low and medium power application, the experimental results indicate that good dynamic response and reduced harmonic distortion can be achieved by increasing switching frequency.