• IEIE Transactions on Smart Processing and Computing
• /
• v.5 no.1
• /
• pp.35-42
• /
• 2016

Developments in power electronics have enabled the widespread application of Pulse Width Modulation (PWM) inverters, notably for connecting renewable systems to the grid. This study demonstrates that a high-quality power can be achieved using a stand-alone inverter, whereby the comparison between the power quality of the stand-alone inverter with battery storage (off-grid) and the power quality of the utility network is presented. Multi-loop control techniques for a single phase stand-alone inverter are used. A capacitor current control is used to give active damping and enhance the transient and steady state inverter performance. A capacitor current control is cheaper than the inductor current control, where a small current sensing resistor is used. The output voltage control is used to improve the system performance and also control the output voltage. The inner control loop uses a proportional gain current controller and the outer loop is implemented using internal model control proportional-integral-derivative to ensure stability. The optimal controls are achieved by using the Sisotool tool in MATLAB/Simulink. The outcome of the control scheme of the numerical model of the stand-alone inverter has a smooth and good dynamic performance, but also a strong robustness to load variations. The numerical model of the stand-alone inverter and its power quality are presented, and the power quality is shown to meet the IEEE 519-2014. Furthermore, the power quality of the off-grid system is measured experimentally and compared with the grid power, showing power quality of off-grid system to be better than that of the utility network.

• Smart Media Journal
• /
• v.4 no.2
• /
• pp.55-61
• /
• 2015

A bandwidth-enhanced ultra-wide band (UWB) CMOS balun-LNA is implemented as a part of a software defined radio (SDR) receiver which supports multi-band and multi-standard. The proposed balun-LNA is composed of a single-to-differential converter, a differential-to-single voltage summer with inductive shunt peaking, a negative feedback network, and a differential output buffer with composite common-drain (CD) and common-source (CS) amplifiers. By feeding the single-ended output of the voltage summer to the input of the LNA through a feedback network, a wideband balun-LNA exploiting negative feedback is implemented. By adopting a source follower-based inductive shunt peaking, the proposed balun-LNA achieves a wider gain bandwidth. Two LNA design examples are presented to demonstrate the usefulness of the proposed approach. The LNA I adopts the CS amplifier with a common gate common source (CGCS) balun load as the S-to-D converter for high gain and low noise figure (NF) and the LNA II uses the differential amplifier with the ac-grounded second input terminal as the S-to-D converter for high second-order input-referred intercept point (IIP2). The 3 dB gain bandwidth of the proposed balun-LNA (LNA I) is above 5 GHz and the NF is below 4 dB from 100 MHz to 5 GHz. An average power gain of 18 dB and an IIP3 of -8 ~ -2 dBm are obtained. In simulation, IIP2 of the LNA II is at least 5 dB higher than that of the LNA I with same power consumption.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.7 no.4
• /
• pp.346-352
• /
• 2002

A novel Zero Current Switching(ZCS) Pulse Width Modulation(PWM) boost converter with dual mode for reducing two rectifiers reverse recovery related losses is proposed. The switches of the proposed converter are operating to work alternatively turn-on and turn-off with soft switching condition In the every cycle and the proposed converter reduces the reverse recovery current, which is related switching losses and EMI problems, of the free-wheeling diode$(D_1, D_2)$ by adding the resonant inductor Lr, in series with the switch $S_1$. The switching components$(S_1, S_2, D, D_1)$ in the proposed boost converter are subjected to minimum voltage and current stresses same as those in their PWM counterparts because there are no additional active switches and resonant elements compared with the conventional ZVT PWM $converters^{[2]}$. The operation of the proposed converter, in this paper, is analyzed and to verify the feasibility of the characteristics is built and tested.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.8 s.338
• /
• pp.53-60
• /
• 2005

Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.2
• /
• pp.162-172
• /
• 2011

In this paper, a design and fabrication of 4 W power amplifier for the WiMAX frequency band(2.3~2.7 GHz) are presented. The adopted active device is a commercially available GaN HEMT chip of Triquint Company, which is recently released. The optimum input and output impedances are extracted for power amplifier design using a specially self-designed tuning jig. Using the adopted impedances value, class-F power amplifier was designed based on EM simulation. For integration and matching in the small package module, spiral inductors and interdigital capacitors are used. The fabricated power amplifier with $4.4{\times}4.4\;mm^2$ shows the efficiency above 50 % and harmonic suppression above 40 dBc for second(2nd) and third(3rd) harmonic at the output power of 36 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.2
• /
• pp.199-207
• /
• 2011

A Ku-band low noise amplifier has been designed and fabricated by using 0.25 um SiGe BiCMOS process. The developed Ku-band LNA RFIC which has been designed with hetero-junction bipolar transistor(HBT) in the BiCMOS process have noise figure about 2.0 dB and linear gain over 19 dB in the frequency range from 9 GHz to 14 GHz. Optimization technique for p-tap value and electro-magnetic(EM) simulation technique had been used to overcome the inaccuracy in the PDK provided from the foundry service company and to supply the insufficient inductor library. The finally fabricated low noise amplifier of two fabrication runs has been implemented with the size of $0.65\;mm{\times}0.55\;mm$. The pure amplifier circuit layout with the reduced size of $0.4\;mm{\times}0.4\;mm$ without the input and output RF pads and DC bais pads has been incorporated as low noise amplication stages in the multi-function RFIC for the active phased array antenna of Ku-band satellite VSAT.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2018.10a
• /
• pp.31-34
• /
• 2018

This paper presents a low-power buck-boost converter for multi-input energy harvesting systems. The designed circuit combines the energy harvested from three input channels in real time and stores it in a storage capacitor. The structure of the buck-boost converter is simplified by using one external inductor and applying time division technique using an arbiter. In addition, to improve the efficiency of the system, the controller circuits of the converter are designed so that current consumption is minimized. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. Simulation results show that the designed circuit consumes up to 490nA of current when all three input channels are active, and the maximum power efficiency is 92%. The chip area of the designed circuit is $1310{\mu}m{\times}1100{\mu}m$.

• Journal of Power Electronics
• /
• v.5 no.3
• /
• pp.233-239
• /
• 2005

In this paper, a new conceptual circuit configuration of a 3-phase voltage source, soft switching AC-DC-AC converter using an IGBT module, which has one ARCPL circuit and one ARDCL circuit, is presented. In actuality, the ARCPL circuit is applied in the 3-phase voltage source rectifier side, and the ARDCL circuit is in the inverter side. And more, each power semiconductor device has a novel clamp snubber circuit, which can save the power semiconductor device from voltage and current across each power device. The proposed soft switching circuits have only two active power semiconductor devices. These ARCPL and ARDCL circuits consist of fewer parts than the conventional soft switching circuit. Furthermore, the proposed 3-phase voltage source soft switching AC-DC-AC power conversion system needs no additional sensor for complete soft switching as compared with the conventional 3-phase voltage source AC-DC-AC power conversion system. In addition to this, these soft switching circuits operate only once in one sampling term. Therefore, the power conversion efficiency of the proposed AC-DC-AC converter system will get higher than a conventional soft switching converter system because of the reduced ARCPL and ARDCL circuit losses. The operation timing and terms for ARDCL and ARCPL circuits are calculated and controlled by the smoothing DC capacitor voltage and the output AC current. Using this control, the loss of the soft switching circuits are reduced owing to reduced resonant inductor current in ARCPL and ARDCL circuits as compared with the conventional controlled soft switching power conversion system. The operating performances of proposed soft switching AC-DC-AC converter treated here are evaluated on the basis of experimental results in a 50kVA setup in this paper. As a result of experiment on the 50kVA system, it was confirmed that the proposed circuit could reduce conduction noise below 10 MHz and improve the conversion efficiency from 88. 5% to 90.5%, when compared with the hard switching circuit.

• Journal of Power Electronics
• /
• v.17 no.4
• /
• pp.942-952
• /
• 2017

Modular multilevel converters (MMCs) have been receiving extensive research interest in high/medium-voltage applications due to its modularity, scalability, reliability, high-voltage capability, and excellent harmonic performance. Submodule capacitors are usually rather bulky because they have to withstand fundamental frequency voltage fluctuations. To reduce the capacitance of these capacitors, this study proposes a modified MMC with an active power decoupling circuit within each submodule. The modified submodule contains an auxiliary half bridge, with its capacitor split in two. Also, the midpoints of the half bridge and the split capacitors are connected by an inductor. With this modified submodule, the fundamental frequency voltage fluctuation can be suppressed to a great extent. The second-order voltage fluctuation, which is the second most significant component in submodule voltage fluctuations, is removed by the proper control of the second-order circulating current. Consequently, the submodule capacitance is significantly reduced. The viability and effectiveness of the proposed new MMC are confirmed by the simulation and experimental results. The proposed MMC is best suited for medium-voltage applications where power density is given a high priority.

• Journal of IKEEE
• /
• v.23 no.3
• /
• pp.858-864
• /
• 2019

A clock system is proposed to eliminate data loss due to frequency difference between sensor nodes in a sensor utility network. The proposed clock system for each sensor node consists of a bust clock-data recovery (CDR) circuit, a digital phase-locked loop outputting a 32-phase clock, and a digital frequency synthesizer using a programmable open-loop fractional divider. A CMOS oscillator using an active inductor is used instead of a burst CDR circuit for the first sensor node. The proposed clock system is designed by using a 65 nm CMOS process with a 1.2 V supply voltage. When the frequency error between the sensor nodes is 1%, the proposed burst CDR has a time jitter of only 4.95 ns with a frequency multiplied by 64 for a data rate of 5 Mbps as the reference clock. Furthermore, the frequency change of the designed digital frequency synthesizer is performed within one period of the output clock in the frequency range of 100 kHz to 320 MHz.