• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.743-746
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• 2003

We have successfully used hydrophobic direct-wafer bonding, along with H-induced layer splitting of Ge, to transfer 700nm think, single-crystal Ge films to Si substrates. Optical and electrical properties have been also observed on these samples. Triple-junction solar cell structures gown on these Ge/Si heterostructure templates show comparable photoluminescence intensity and minority carrier lifetime to a control structure grown on bulk Ge. When heavily doped p$^{+}$Ge/p$^{+}$Si wafer bonded heterostructures were bonded, ohmic interfacial properties with less than 0.3Ω$\textrm{cm}^2$ specific resistance were observed indicating low loss thermal emission and tunneling processes over and through the potential barrier. Current-voltage (I-V) characteristics in p$^{+}$Ge/pSi structures show rectifying properties for room temperature bonded structures. After annealing at 40$0^{\circ}C$, the potential barrier was reduced and the barrier height no longer blocks current flow under bias. From these observations, interfacial atomic bonding structures of hydrophobically wafer bonded Ge/Si heterostructures are suggested.ested.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.318-321
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• 2002

This paper presents a proper condition to achieve high conversion efficiency using PC1D simulator on sri-crystalline Si solar cells. Various efficiency influencing parameters such as rear surface recombination velocity and minority carrier diffusion length in the base region, front surface recombination velocity, junction depth and doping concentration in the Emitter layer, BSF thickness and doping concentration were investigated. Optimized cell parameters were given as rear surface recombination of 1000 cm/s, minority carrier diffusion length in the base region 200 $\mu\textrm{m}$, front surface recombination velocity 100 cm/s, sheet resistivity of emitter layer 100 Ω/$\square$, BSF thickness 5 $\mu\textrm{m}$, doping concentration 5${\times}$10$\^$19/ cm$\^$-3/. Among the investigated variables, we learn that a diffusion length of base layer acts as a key factor to achieve conversion efficiency higher than 19 %.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.62.2-62.2
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• 2010

박막 실리콘 태양 전지는 저가격화 및 대량생산, 대면적화에 유리하다는 장점을 가지고 있다. 단점으로 지적되는 낮은 효율을 극복하기 위해 광흡수층의 밴드갭이 서로 다른 두 개 이상의 박막을 적층하여, 넓은 파장 대역의 빛을 효과적으로 흡수함으로써 광변환 효율을 올리기 위한 많은 연구가 이루어지고 있다. 서로 다른 밴드갭의 광흡수층을 가진 p-i-n 구조를 다중 적층하여 고효율의 태양 전지를 제작하기 위해서는 n-도핑층과, p-도핑층 간에 전자와 정공이 빠르게 재결합할 수 있는 터널 접합(Tunnel Recombination Junction)의 형성이 필수적이며, 이때 광손실이 최소화되도록 해야한다. 만약 터널 접합이 적절하게 형성되지 않으면 결합되지 않은 전자와 정공이 도핑층 사이에 쌓이게 되고, 도핑층 사이의 저항 증가로 태양 전지의 광변환 효율은 크게 하락한다. 이번 연구에서는 터널 접합이 잘 이루어지게 하기 위한 n-도핑층 및 p-도핑층 박막의 특성과, 터널 접합의 특성에 따른 적층형 태양 전지의 광효율 변화를 확인하였다. 광흡수층 및 도핑층은 TCO($SnO_2:F$, Asahi) 유리 기판 위에 PECVD를 사용하여 p-i-n 구조로 RF Power 조건에서 증착되었고, ${\mu}c$-Si 광흡수층의 경우에는 VHF Power 조건에서 증착되었다. 광흡수층이 a-Si/${\mu}c$-Si의 구조를 가지는 이중 접합 태양 전지에서 ${\mu}c$-Si n-도핑층/${\mu}c$-Si p-도핑층 사이의 터널 접합 실험 결과 n-도핑층 및 p-도핑층의 결정화도와 도핑 농도를 조절하여 터널 접합의 저항을 최소화했고, 터널 접합 특성이 이중 접합 셀의 광효율 특성과 유사한 경향을 보임을 확인하였다. 광흡수층이 a-Si/a-SiGe/${\mu}c$-Si의 구조를 가지는 삼중 접합 태양 전지 실험의 경우 a-Si과 a-SiGe 광흡수층 사이에 ${\mu}c$-Si n-도핑층/${\mu}c$-Si p-도핑층/a-SiC p-도핑층의 구조를 적용하여 터널 접합을 형성하였으며, ${\mu}c$-Si p-도핑층의 두께 및 박막 특성을 개선하여 광손실이 최소화된 터널 접합을 구현하였고, 삼중 접합 태양 전지에 적용되었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.20-20
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• 2010

Organic based photovoltaics (OPV) have been received a lot of attention because they are lightweight, inexpensive to fabricate and flexible compare to crystalline Si solar cells. In this seminar, several important progresses in the Polymer PV, such as, formation of bulk heterojunction, development of post annealing technique, tandem cell fabrication will be introduced. In addition that, some efforts to achieve the further improvement in the performance of the Polymer PV will be discussed.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.22 no.2
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• pp.65-72
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• 2012

Aluminum induced crystallization of amorphous silicon was attempted by the aluminum substrate. To avoid the layer exchange between silicon and aluminum layer, Ni layer was deposited between these two layers by sputtering. To obtain the bigger grain of the crystalline silicon, wet blasted silica layer was employed as windows between the nickel and a-Si layer. Ni obtained after the annealing treatment at $520^{\circ}C$ was found to be a promising material for the diffusion barrier between silicon and aluminum. One way to obtain bigger grain of crystalline silicon layer applicable to solar cell of higher performance was envisioned in this investigation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.249-249
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• 2010

We investigated novel surface treatment and its impact on silicon photovoltaic cells. Using 2-step etching methods, we have changed the nanostructure on pyramid surface so that less light is reflected. This work proposes an improved texturing technique of mono crystalline silicon surface for solar cells with sub-nanotexturing process. The nanotextured silicon surface exhibits a lower average reflectivity (~4%) in the wavelength range of 300-1100nm without antireflection coating layer. It is worth mentioning that the surface of pyramids may also affect the surface reflectance and carrier lifetime. In one word, we believe nanotextruing is a promising guide for texturization of monocrystalline silicon surface.

• Current Photovoltaic Research
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• v.7 no.4
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• pp.111-120
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• 2019

The output power of a crystalline silicon (c-Si) photovoltaic (PV) module is not directly the sum of the powers of its unit cells. There are several losses and gain mechanisms that reduce the total output power when solar cells are encapsulated into solar modules. Theses factors are getting high attention as the high cell efficiency achievement become more complex and expensive. More research works are involved to minimize the "cell-to-module" (CTM) loss. Our paper is aimed to focus on electrical losses due to interconnection and mismatch loss at PV modules. Research study shows that among all reasons of PV module failure 40.7% fails at interconnection. The mismatch loss in modern PV modules is very low (nearly 0.1%) but still lacks in the approach that determines all the contributing factors in mismatch loss. This review paper is related to study of interconnection loss technologies and key factors contributing to mismatch loss during module fabrication. Also, the improved interconnection technologies, understanding the approaches to mitigate the mismatch loss factors are precisely described here. This research study will give the approach of mitigating the loss and enable improvement in reliability of PV modules.

• Korean Journal of Materials Research
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• v.26 no.8
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• pp.401-405
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• 2016

The cobalt silicides were investigated for employment as a catalytic layer for a DSSC. Using an E-gun evaporation process, we prepared a sample of 100 nm-thick cobalt on a p-type Si (100) wafer. To form cobalt silicides, the samples were annealed at temperatures of $300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$ for 30 minutes in a vacuum. Four-point probe, XRD, FE-SEM, and CV analyses were used to determine the sheet resistance, phase, microstructure, and catalytic activity of the cobalt silicides. To confirm the corrosion stability, we also checked the microstructure change of the cobalt silicides after dipping into iodide electrolyte. Through the sheet resistance and XRD results, we determined that $Co_2Si$, CoSi, and $CoSi_2$ were formed successfully by annealing at $300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$, respectively. The microstructure analysis results showed that all the cobalt silicides were formed uniformly, and CoSi and $CoSi_2$ layers were very stable even after dipping in the iodide electrolyte. The CV result showed that CoSi and $CoSi_2$ exhibit catalytic activities 67 % and 54 % that of Pt. Our results for $Co_2Si$, CoSi, and $CoSi_2$ revealed that CoSi and $CoSi_2$ could be employed as catalyst for a DSSC.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.55-60
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• 2012

In order to develop electroless-plated Nickel Phosphate (Ni-P) as a contact material for high efficient low-cost silicon solar cells, we evaluated the effect of ambient thermal annealing on the degradation behavior of interfacial adhesion energy between electroless-plated Ni-P and silicon solar cell wafers by applying 4-point bending test method. Measured interfacial adhesion energies decreased from 14.83 to 10.83 J/$m^2$ after annealing at 300 and $600^{\circ}C$, respectively. The X-ray photoelectron spectroscopy analysis suggested that the bonding interface was degraded by environmental residual oxygen, in which the oxidation inhibit the stable formation of Ni silicide phase between electroless-plated Ni-P and silicon interface.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.458.1-458.1
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• 2014

An effective light-managing structure has been achieved by using a nano-imprint method. A transparent conductor of indium-tin-oxide (ITO) was periodically nanodome-shaped to have a height of 200 nm with a diameter of 340 nm on a p-type Si substrate. This spontaneously formed a heterojunction between the ITO layer and Si substrate and effectively reduced the light-reflection. The ITO nanodome device response was significantly enhanced to 6010 from the value of 72.9 of a planar ITO film. The transparent conducting ITO nanodome structure efficiently manipulates the incident light driving into the light-absorber and can be applied in various photoelectric applications.