• Journal of Advanced Navigation Technology
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• v.20 no.6
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• pp.631-637
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• 2016

Quantum cellular automata (QCA) are one of the alternative technologies that can overcome the limits of complementary metal-oxide-semiconductor (CMOS) scaling. It consists of nano-scale cells and demands very low power consumption. Various circuits on QCA have been researched until these days, and in the middle of the researches, exclusive-OR (XOR) gates are used as error detection and recover. Typical XOR logic gates have a lack of scalable, many clock zones and crossover designs so that they are difficult to implement. In order to overcome these disadvantages, this paper proposes XOR design using majority gate reduced clock zone. The proposed design is compared and analysed to previous designs and is verified the performance.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.1-8
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• 1998

In this paper, we designed a low power 8bit ELM adder with static CMOS and hybrid logic styles on a chip. The designed 8bit ELM adder with both logic styles was fabricated in a 0.8$\mu\textrm{m}$ single-poly double-metal, LG CMOS process and tested. Hybrid logic style consists of CCPL(Combinative Complementary Pass-transistor Logic), Wang's XOR gate and static CMOS for critical path which determines the speed of ELM adder. As a result of chip test, the ELM adder with hybrid logic style is superior to the one with static CMOS by 9.29% in power consumption, 14.9% in delay time and 22.8% in PDP(Power Delay Product) at 5.0V supply voltage, respectively.

• Journal of Electrical Engineering and information Science
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• v.3 no.1
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• pp.8-13
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• 1998

Often ESOP(Exclusive Sum of Products) expressions provide more compact representations of logic functions and implemented circuits are known to be highly testable. Motivated by the merits of using XOR(Exclusive-OR) gates in circuit design, ESOP(Exclusive Sum of Products) expressions are considered s the input to the logic synthesis for random pattern testability. The problem of interest in this paper is whether ESOP expressions provide better random testability than corresponding SOP expressions of the given function. Since XOR gates are used to collect product terms of ESOP expression, fault propagation is not affected by any other product terms in the ESOP expression. Therefore the test set for a fault in ESOP expressions becomes larger than that of SOP expressions, thereby providing better random testability. Experimental results show that in many cases, ESOP expressions require much less random patterns compared to SOP expressions.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.301-310
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• 2017

Quantum-dot cellular automata(QCA) is an alternative technology for implementing various computation, high performance, and low power consumption digital circuits at nano scale. In this paper, we propose a new universal gate in QCA. By using the universal gate, we propose a novel XOR gate which is reduced time/hardware complexity. The universal gate can be used to construct all other basic logic gates. Meanwhile, the proposed universal gate is designed by basic cells and a rotated cell. The rotated cell of the proposed universal gate is located at the central of 3-input majority gate structure. In this paper, we propose an XOR gate using three universal gates, although more than five 3-input majority gates are used to design an XOR gate using the 3-input majority gate. The proposed XOR gate is superior to the conventional XOR gate in terms of the total area and the consumed clock because the number of gates are reduced.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.291-300
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• 2017

Quantum-dot cellular automata(QCA) is a computing model designed to be similar to cellular automata, and an alternative technology for next generation using high performance and low power consumption. QCA is undergoing various studies with recent experimental results, and it is one of the paradigms of transistors that can solve device density and interconnection problems as nano-unit materials. An XOR gate is a gate that operates so that the result is true when either one of the logic is true. The proposed XOR gate consists of five layers. The first layer consists of OR gates, the third and fifth layers consist of AND gates, and the second and fourth layers are designed as passages in the middle. The half adder consists of an XOR gate and an AND gate. The proposed half adder is designed by adding two cells to the proposed XOR gate. The proposed half adder consists of fewer cells, total area, and clock than the conventional half adder.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.6
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• pp.1443-1454
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• 2016

Balanced encoding method that implement Dual-rail logic style based on hardware technique to software is efficient countermeasure against side-channel analysis without additional memory. Since balanced encoding keep Hamming weight and/or Hamming distance of intermediate values constantly, using this method can be effective as countermeasure against side channel analysis due to elimination of intermediate values having HW and/or HD relating to secret key. However, former studies were presented for Constant XOR operation, which can only be applied to crypto algorithm that can be constructed XOR operation, such as PRINCE. Therefore, our first proposal of new Constant ADD, Shift operations can be applied to various symmetric crypto algorithms based on ARX. Moreover, we did not used look-up table to obtain efficiency in memory usage. Also, we confirmed security of proposed Constant operations with Mutual Information Analysis.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.2
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• pp.351-356
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• 2022

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.10a
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• pp.25-27
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• 1984

Using LED sources, the system that performs optical logic function of the input data arrays will be presented. Sixteen possible functions of two binary data arrays, such as AND, OR, NOR and XOR are simply obtained in parallel by controlling LED switching mode. Experimental result and some examples of application will be given.

• Journal of IKEEE
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• v.18 no.3
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• pp.328-334
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• 2014

This paper proposes an optical encryption and decryption system for OFB(Output Feedback Block) encryption algorithm. The proposed scheme uses a dual-encoding technique in order to implement optical XOR logic operation. Also, the proposed method provides more enhanced security strength than the conventional electronic OFB method due to the huge security key with 2-dimensional array. Finally, computer simulation results of encryption and decryption are shown to verify the proposed method, and hence the proposed method makes it possible to implement more effective and stronger optical block encryption system with high-speed performance and the benefits of parallelism.

• Journal of Advanced Navigation Technology
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• v.18 no.2
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• pp.178-184
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• 2014

CMOS technology based on PCA is very efficient at an implementation of memory or ALU. However, there has been a growing interest in quantum-dot cellular automata (QCA) because of the limitation of CMOS scaling. In this paper, we propose a design of PCA architecture based on QCA. In the proposed PCA design, we utilize D flip-flop and XOR logic gate without wire crossing technique, and design a input and rule control switches. In experiment, we perform the simulation of the proposed PCA architecture by QCADesigner. As the result, we confirm the efficiency the proposed architecture.