• Journal of Computing Science and Engineering
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• v.4 no.2
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• pp.128-152
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• 2010

With the advance of computer and communication technologies, wireless sensor networks (WSNs) are increasingly used in many aspects of our daily life. However, since the battery lifetime of WSN nodes is restricted, the WSN lifetime is also limited. Therefore, it is crucial to determine this limited lifetime in advance for preventing service interruptions in critical applications. This paper proposes a feasible static analysis approach to estimating the worstcase lifetime of a WSN. Assuming known routes with a given sensor network topology and SMAC as the underlying MAC protocol, we statically estimate the lifetime of each sensor node with a fixed initial energy budget. These estimations are then compared with the results obtained through simulation which run with the same energy budget on each node. Experimental results of our research on TinyOS applications indicate that our approach can safely and accurately estimate worst-case lifetime of the WSN. To the best of our knowledge, our work is the first one to estimate the worst-case lifetime of WSNs through a static analysis method.

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.5
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• pp.91-101
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• 2014

In this study, we presented a timing verification method for a passenger car diesel engine management system (EMS) using measurement-based worst-case execution time (WCET) analysis. In order to cope with AUTOSAR-compliant software architecture, a development process model is proposed. In the process model, a runnable is regarded as a test unit and its temporal behavior (i.e. maximum observed execution time, MOET) is obtained along with on-target functionality evaluation results during online unit test. Furthermore, a cost-effective framework for online unit test is proposed. Because the runtime environment layer and the standard calibration environment are utilized to implement test interface, additional resource consumption of the target processor is minimized. Using the proposed development process model and unit test framework, the MOETs of 86 runnables for diesel EMS are obtained with 213 unit test cases. Using the obtained MOETs of runnables, the WCETs of tasks are estimated and the schedulability is evaluated. From the schedulability analysis results, the problems of the initially designed schedule table is recognized and it is fixed by redesigning of the runnable mapping and task offset. Through the various test scenarios, the proposed method is validated.

• Journal of Computing Science and Engineering
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• v.7 no.4
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• pp.285-299
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• 2013

To enable hard real-time systems to take advantage of multicore processors, it is crucial to obtain the worst-case execution time (WCET) for programs running on multicore processors. However, this is challenging and complicated due to the inter-thread interferences from the shared resources in a multicore processor. Recent research used the combined cache conflict graph (CCCG) to model and compute the worst-case inter-thread interferences on a shared L2 cache in a multicore processor, which is called the CCCG-based approach in this paper. Although it can compute the WCET safely and accurately, its computational complexity is exponential and prohibitive for a large number of cores. In this paper, we propose three counter-based approaches to significantly reduce the complexity of the multicore WCET analysis, while achieving absolute safety with tightness close to the CCCG-based approach. The basic counter-based approach simply counts the worst-case number of cache line blocks mapped to a cache set of a shared L2 cache from all the concurrent threads, and compares it with the associativity of the cache set to compute the worst-case cache behavior. The enhanced counter-based approach uses techniques to enhance the accuracy of calculating the counters. The hybrid counter-based approach combines the enhanced counter-based approach and the CCCG-based approach to further improve the tightness of analysis without significantly increasing the complexity. Our experiments on a 4-core processor indicate that the enhanced counter-based approach overestimates the WCET by 14% on average compared to the CCCG-based approach, while its averaged running time is less than 1/380 that of the CCCG-based approach. The hybrid approach reduces the overestimation to only 2.65%, while its running time is less than 1/150 that of the CCCG-based approach on average.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.15-25
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• 2005

Embedded systems have a set of tasks to execute. These tasks can be implemented either on application specific hardware or as software running on a specific processor. The design of an embedded system involves the selection of hardware software resources, Partition of tasks into hardware and software, and performance evaluation. An accurate estimation of execution time for extreme cases (best and worst case) is important for hardware/software codesign. A tighter estimation of the execution time bound nay allow the use of a slower processor to execute the code and may help lower the system cost. In this paper, we consider an ARM-based embedded system and developed a tool to estimate the tight boundary of execution time of a task with loop bounds and any additional program path information. The tool we developed is based on an exiting timing analysis tool named 'Cinderella' which currently supports i960 and m68k architectures. We add a module to handle ARM ELF object file, which extracts control flow and debugging information, and a module to handle ARM instruction set so that the new tool can support ARM processor. We validate the tool by comparing the estimated bound of execution time with the run-time execution time measured by ARMulator for a selected bechmark programs.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.6
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• pp.549-557
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• 2000

Distributed Memory Machine(DMM) is necessary for the effective computation of the data which is complicated and very large. Task scheduling is a method that reduces the communication time among tasks to reduce the total execution time of application program and is very important for the improvement of DMM. Task Duplicated based Scheduling(TDS) method improves execution time by reducing communication time of tasks. It uses clustering method which schedules tasks of the large communication time on the same processor. But there is a problem that cannot optimize communication time between task sending data and task receiving data. Hence, this paper proposes a new method which solves the above problem in TDS. Modified Task Duplicated based Scheduling(MTDS) method which can approximately optimize the communication time between task sending data and task receiving data by checking the optimal condition, resulted in the minimization of task execution time by reducing the communication time among tasks. Also system modeling shows that task execution time of MTDS is about 70% faster than that of TDS in the best case and the same as the result of TDS in the worst case. It proves that MTDS method is better than TDS method.

• International Journal of Automotive Technology
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• v.5 no.4
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• pp.269-276
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• 2004

There has been considerable activity in recent years in developing timing analysis algorithms for distributed real-time control systems. However, it is difficult for control engineers to analyze the timing behavior of distributed real-time control systems because the algorithms was developed in a software engineer's position and the calculation of the algorithm is very complex. Therefore, there is a need to develop a timing analysis tool, which can handle the calculation complexity of the timing analysis algorithms in order to help control engineers easily analyze or develop the distributed real-time control systems. In this paper, an interactive timing analysis tool, called RAT (Response-time Analysis Tool), is introduced. RAT can perform the schedulability analysis for development of distributed real-time control systems. The schedulability analysis can verify whether all real-time tasks and messages in a system will be completed by their deadlines in the system design phase. Furthermore, from the viewpoint of end-to-end scheduling, RAT can perform the schedulability analysis for series of tasks and messages in a precedence relationship.

• Transactions of the Korean Society of Automotive Engineers
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• v.13 no.1
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• pp.194-203
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• 2005

The process of guaranteeing that a distributed real-time control system will meet its timing constraints, is referred to as schedulability analysis. However, schedulability analysis algorithm cannot be simply used to analyze the system because of complex calculations of algorithm. It is difficult for control engineer to understand the algorithm because it was developed in a software engineer's position. In this paper we introduce a Response-time Analysis Tool(RAT) which provides easy way far system designer to analyze the system by encapsulating calculation complexity. Based on the RAT, control engineer can verify whether all real-time tasks and messages in a system will be completed by their deadline in the system design phase.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.184-186
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• 2004

검사점 작성을 이용하는 실시간 태스크의 스케줄링 가능성을 알기 위한 선행 조건으로 최악 수행시간을 분석하고 이를 최소로 하는 효율적인 검사점 작성의 위치를 결정하는 방법을 제시한다. 여기서 사용하는 조건은 k 개의 연속적인 결함을 허용하고 태스크의 검사점 작성 비용이 고정적인 경우와 가변적인 경우를 가정한다. 이러한 각 조건에서 최악 수행 시간을 최소로 하는 검사점 작성 알고리즘을 제시한다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.2 s.308
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• pp.12-20
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• 2006

In scheduling of real-time tasks, the required hardware performance for a given set of tasks is determined based on the worst case execution time. For soft real-time tasks as multimedia applications, a lower performance hardware can service the tasks. Since the execution time of a task can vary in time, we can reclaim the slacks of early completed tasks for those of longer than average execution times. Then, the average ratio of deadline-miss can be lowered. This paper presents an algorithm, Aggressive Slack Reclamation (ASR), that tasks share slacks aggressively. A simulation result shows that ASR enhances the deadline-miss ratio and number of context switches than previous results.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.271-281
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• 2007

Real-time support of embedded OS is not optional, but essential in contemporary embedded systems. In order to achieve these system#s real-time property, it is crucial that schedulability analysis for tasks having its property have been accomplished before system execution. Acquiring Worst-Case Execution Time(WCET) of task is a core part of schedulability analysis. Because traditional WCET tools analyze only its estimation of application task(i.e. program), it is not considered that application tasks are affected by scheduling primitives(e.g. scheduler, interrupt service routine, etc.) of OS when it schedules them. In this paper, we design and implement WCET analysis tool which deliberates on scheduling primitives of system using embedded Linux widely used in embedded OSes. This tool can estimate either WCET of normal application programs or corresponding primitives which have an influence on schduling property in embedded Linux kernel. Therefore, precision of estimation about schedulability analysis is improved. We develop this tool as Eclipse#s plug-in to work properly in any platform and support convenient interface or functionality for user.