• 제목/요약/키워드: Wire coating

검색결과 114건 처리시간 0.021초

NBR/PVC의 polymer blend에 관(關)한 연구(硏究)(제2보(第2報)) (Studies on NBR/PVC polymer blend (part 2))

  • 허동섭;이정근
    • Elastomers and Composites
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    • 제6권1호
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    • pp.71-81
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    • 1971
  • The intention of this study is to investigate the properties of polymer blend, NBR/PVC vulcanizates and blending procedures such as roll-mixing temperatures and sequences for polymer blending of NBR and PVC(resin type). The results obtained are as follows: 1. The roll temperature applied for polymer blending is around $150^{\circ}C$. At this temperature region, the degradation of rubber stock, which may be caused by heat, can be minimized and mill processing in practical application in industries can also be facilitated. 2. It is obviously necessary that a small amount of plasticizers should be added to the stock for improving processibility of roll mixing and physical properties. 3. On roll-mixing sequence, it is more effective that PVC compounded with plasticizer is added to NBR milled on hot roll. 4. The vulcanizates of the blends with different degree of polymerization of PVC ale similar to one another in properties. 5. NBR/PVC(70/30) blends shows the better physical characters than eve,-made foreign latex blend except abrasion-resistance. 6. As PVC addition ratio is increased, the physical properties such as resistance to ozone, tear, heat and oil and tensile strength, modulus, hardness have also improved, on the other hand, tension set and rebound character decreased. 7. The curve of ultimate elongation have point of inflection at the ratio of $30\sim40$ part of PVC. 8. While CR is blended, the physical properties such as brittle point, rebound and resistance to oil in high temperature have improved. 9. Polymer blend of NBR and domestic PVC is applied for the industrial utility such as rubber sole and heel, electric wire cover and oil-resistant packing, coating and gasket, printing roll, film for food packing etc.

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Development of exothermic system based on internet of things for preventing damages in winter season and evaluation of applicability to railway vehicles

  • Kim, Heonyoung;Kang, Donghoon;Joo, Chulmin
    • Smart Structures and Systems
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    • 제29권5호
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    • pp.653-660
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    • 2022
  • Gravel scattering that is generated during operation of high-speed railway vehicle is cause to damage of vehicle such as windows, axle protector and so on. Especially, those are frequently occurred in winter season when snow ice is generated easily. Above all, damage of vehicle windows has not only caused maintenance cost but also increased psychological anxiety of passengers. Various methods such as heating system using copper wire, heating jacket and heating air are applied to remove snow ice generated on the under-body of vehicle. However, the methods require much run-time and man power which can be low effectiveness of work. Therefore, this paper shows that large-area heating system was developed based on heating coat in order to fundamentally prevent snow ice damage on high-speed railway vehicle in the winter season. This system gives users high convenience because that can remotely control the heating system using IoT-based wireless communication. For evaluating the applicability to railroad sites, a field test on an actual high-speed railroad operation was conducted by applying these techniques to the brake cylinder of a high-speed railroad vehicle. From the results, it evaluated how input voltage and electric power per unit area of the heating specimen influences exothermic performance to draw the permit power condition for icing. In the future, if the system developed in the study is applied at the railroad site, it may be used as a technique for preventing all types of damages occurring due to snow ice in winter.

LSM이 코팅된 고체산화물 연료전지용 Crofer Mesh 집전체 개발 (Development of LSM-Coated Crofer Mesh for Current Collectors in Solid Oxide Fuel Cells)

  • 백주열;박석주;이승복;이종원;임탁형;송락현;김광범;신동열
    • 전기화학회지
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    • 제13권4호
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    • pp.256-263
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    • 2010
  • 본 연구에서는 고체산화물 연료전지의 공기극 집전체로 사용되고 있는 고가의 Ag 소재를 대체하고자 전도성 세라믹이 코팅된 mesh 형태의 Crofer 22 APU 집전체를 개발하였다. 고전자전도성의 $(La_{0.80}Sr_{0.20})_{0.98}MnO_3$ (LSM)을 습식 스프레이법으로 코팅하여 고온 산화 및 전기적 특성의 열화를 억제하고자 하였다. $800^{\circ}C$의 산화 실험 결과에 의하면 LSM이 코팅된 Crofer mesh의 면저항(area-specific resistance)은 mesh의 제작에 사용된 와이어 지름과 접촉 부위의 형상등 실제 접촉점의 수 및 면적을 좌우하는 mesh의 특성에 의해 좌우되었다. 또한 LSM 코팅 후 $H_2/N_2$ 분위기에서의 열처리를 통해 Crofer mesh와 LSM 코팅층 계면에서의 Cr 함유 산화물의 형성을 효과적으로 억제하여 전기적 특성의 열화를 억제할 수 있다.

Copper Interconnection and Flip Chip Packaging Laboratory Activity for Microelectronics Manufacturing Engineers

  • Moon, Dae-Ho;Ha, Tae-Min;Kim, Boom-Soo;Han, Seung-Soo;Hong, Sang-Jeen
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.431-432
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    • 2012
  • In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

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