• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.7-15
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• 2002

The digital DBS tuner is designed and implemented in a CMOS process using a direct-conversion architecture that offers a high degree of integration. To generate mathched LO I/Q quadrature signals covering the total input frequency range, a fully integrated ring oscillator is employed. And, to decrease a high level of phase noise of the ring oscillator, a frequency synthesizer is designed using a double loop strucure. This paper proposes and verifies a band selective loop for fast frequency switching time of the double loop frequency synthesizer. The down-conversion mixer with source follower input stages is used for low voltage operation. An experiment implementation of the frequency synthesizer and mixer with integrated a 0.25um CMOS process achieves a switching time of 600us when frequency changes from 950 to 2150MHz. And, the experiment results show a quadrature amplitude mismatch of max. 0.06dB and a quadrature phase mismathc of max. >$3.4^{\circ}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.2
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• pp.329-337
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• 1999

In this dissertation, the characteristics of W-CDMA(Wideband CDMA) are studied and required specifications of IMT-2000 transceiver using W-CDMA method are proposed. Also, in order to design the RF circuits satisfied the proposed specifications, theoretical models are expanded and real circuits are made. Then the RF circuits of the mobile stations are implemented in the three parts, transmitter, receiver and frequency synthesizer and are evaluated. The frequency synthesizer is designed using techniques of swallow counter and passive 3rd loop filter. For improving characteristics of the loop, a LPF was added to the 2nd loop filter. So although the locking times are loosed, the spurious are reduced. The output power of transmitter is over 50mW, the spurious output is -40dB/30kHz at 5MHz offset and power control range is -20dB at 2.5V. The proposed specifications are considered in highly practical environment and the theoretical designs and the experiments are expressed as simply as possible in order to facilitate understanding. It stands to reason that the results of this study can be used to design the wider CDMA(25MHz Bandwidth) mobile communication systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.117-124
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• 2009

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.291-297
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• 2011

In this paper, the differential quantized method and the parallel method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed And we design the DDFS by FPGA The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is saved by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). Also we design the phase-to-sine converter using the phase accumulator of parallel type for generating the high frequency. So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction and we can design the DDFS generating the high frequency.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.2017-2019
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• 2004

본 논문에서는 S/C-밴드(2${\sim}$8GHz)에서 동작하는 초광대역 주파수 합성기를 설계하였다. 먼저 S-밴드(2-4GHz) 광대역 전압제어발진기를 가지고 획득시간을 단축하기 위한 연산 증폭기를 사용한 DA변환기와 능동루프 필터(Active Loop Filter)로 구성된 S-밴드 주파수 합성기를 설계하였다. 그리고 주파수 체배기, SPDT RF 스위치를 통합하여 최종적으로 S/C-밴드 초광대역 주파수 합성기를 설계하였다. 제작된 주파수 합성기는 200kHz 비교주파수에서 위상잡음은 100kHz 옵셋 주파수에서 -92dBc/Hz이하, 불요주파수 특성은 -62.33dBc 이하, 획득시간은 1.3ms 이하로 측정되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.202-207
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• 2015

A CMOS relaxation oscillator, with high robustness over process, voltage and temperature (PVT) variations, is designed in $0.18{\mu}m$ CMOS. The proposed oscillator, consisting of full-differential charge-discharge timing circuit and switched-capacitor based voltage-to-current conversion, could be expanded to a simple open-loop frequency synthesizer (FS) with output frequency digitally tuned. Experimental results show that the proposed oscillator conducts subcarrier generation for frequency-modulated ultra-wideband (FM-UWB) transmitters with triangular amplitude distortion less than 1%, and achieves frequency deviation less than 8% under PVT and phase noise of -112 dBc/Hz at 1 MHz offset frequency. Under oscillation frequency of 10.5 MHz, the presented design has the relative FS error less than 2% for subcarrier generation and the power dissipation of 0.6 mW from a 1.8 V supply.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.217-218
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• 2008

Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. A general method for achieving both reduced VCO gain(Kvco) and wide frequency band is to use the switched-capacitor bank LC VCO. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO with reduced variation of VCO gain and frequency steps. Buffers, divide-by-2 circuits and control logics the simulation results show that the designed circuit has a phase noise at 100kHz better than -106dBc/Hz throughout the signal band and consumes $9.5{\sim}13mA$ from a 1.8V supply.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.195-196
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• 2007

Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO, five divide-by-2 circuits and several buffers. The simulation results show that the designed circuit has a phase noise at 10kHz better than -87dBc/Hz throughout the signal band and consumes 10mA from a 1.8V supply.