• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.48 no.5
• /
• pp.249-256
• /
• 1999

This paper describes static characteristics analysis of linear pulse motor(LPM) with two permanent magnets. Linear pulse motors are finding a wide range of application for the Factory-Automation or the Office-Automation. Typically, LPM provides for a reliable and precise control of position, velocity, or acceleration without using a closed-loop system. Some of the advantages of LPMs are ease of control, step multiplication, static and dynamic positioning, and locking force. The flux density and thrust of LPM is computed by the FEM and magnetic equivalent circuits which considered the magnetic nonlinear phenomena. The result of characteristics analysis are shown as the flux, the air gap reluctance and the thrust. The velocity and position characteristics as a function of unit step input is measured. To estimate the unit step response charecteristic of LPM, the simulation results by Matlab and the experimental results is compared.

• Proceedings of the IEEK Conference
• /
• 2000.07b
• /
• pp.969-972
• /
• 2000

This paper proposes 1.5V-3GHz CMOS PLL with a new delay cell for operating in high frequency and multi chained two stage VCO to improve phase noise performance. The proposed multi-chained architecture is able to reduce a timing jitter or a transition spacing and the newly VCO is operating in high frequency. The PFD circuit designed to prevent fluctuation of charge pump circuit under the locking condition. Simulation results show that the tuning range of proposed VCO is wide at 1.8GHz-3.2Ghz and power dissipation is 0.6mW.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.37 no.3
• /
• pp.44-54
• /
• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.3
• /
• pp.404-416
• /
• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.12
• /
• pp.65-72
• /
• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.44 no.1
• /
• pp.74-84
• /
• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Korean Journal of Optics and Photonics
• /
• v.15 no.1
• /
• pp.17-21
• /
• 2004

We demonstrate an S/S＋band discretely tunable thulium doped fiber laser (TTDFL), anchored on a 50-㎓ ITU-T grid. Investigating the inversion analysis of the thulium doped fiber (TDF) in applying a dual wavelength (1.4 m and 1.5 m) pumping scheme, a laser whose tuning range covers most of the S/S＋band has been obtained. Within the wide 3-㏈ bandwidth of 65.1 nm, the output power of the tunable laser exceeds 6.1 ㏈m with very flat spectral profile and the number of DWDM channels generated is as large as 178. If we increase the subsidiary pump power to 22 ㎽, the bandwidth is expanded up to 66.2 nm. By controlling the temperature of the fine grid filter, we have also shown that the frequency locking capability of the laser can be improved. The laser developed in this work is expected to be utilized as a practical optical source providing reference wavelengths in the S/S＋band.