• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.571-575
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• 2002

Generation of electrical energy faces many problems today. Solar power converters were used to convert the electrical energy from the solar arrays to a stable and reliable power source. The object of this paper is to analyze and design DC-DC converters in a solar energy system to investigate the performance of the converters. A DC-DC converter can be commonly used to control the power flow from solar cell to load and to achieve maximum power point tracking(MPPT), DC-AC converter can also be used to modulate the DC power to AC power being applied on common utility load. A DC-DC converter is used to boost the solar cell voltage to constant 360(V) DC link and to ensure operation at the maximum power point tracking, If a wide input voltage range has to be covered a boost converter is required. In this paper, author described that simulation and experimental results of PV system contain solar modules, a DC-DC converter(boost type chopper), a DC-AC converter (3-phase inverter) and resistive loads.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.3
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• pp.150-157
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• 2002

This paper presents preliminarily an implementation of digital high-performance motion control system of Reluctance Synchronous Motor (RSM) drives with direct torque control (DTC). The system consist of stator flux observer, torque estimator, two hysteresis band controllers, an optimal switching look-up table, IGBT voltage source inverter, and TMS320F240 DSP controller made by Texas Instruments. The stator fluff observer is based on the combined voltage and current model with stator flux feedback adaptive control, and the input of the observer are the stator voltage and current of motor terminal for wide speed range. The rotor position and speed sensor used 6000 pulse/rev encoder. In order to prove rightness of the suggested control algorithm, we have some simulation and actual experimental system at $\pm$20 and $\pm$2000 rpm. The developed digitally high-performance motion control system+ are shown a good response characteristic of control results and high performance features using 1.0kW RSM which has 2.57 Ld/Lq salient ratio.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.5
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• pp.404-413
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• 2017

This paper suggests an isolated PFC converter for electric vehicle (EV) chargers with wide-output voltage range. The proposed converter is based on voltage-fed full-bridge structure. All the harmonic and output controls are performed by secondary and primary switches are only operated under a fixed frequency with 50% duty-ratio. In addition, harmonic modulation technique is adopted to obtain a near unity power factor without input current monitoring. The feasibility of the proposed charger has been verified with a 10-kW prototype.

• Journal of the Korean Society of Industry Convergence
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• v.20 no.2
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• pp.97-104
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• 2017

In the present industrial field, the demand for the development of the solar power source device and the charging device for the solar cell is gradually increasing. The solar charger is largely divided into a DC-DC converter that converts the voltage generated from the sunlight to a charging voltage, and a battery and a charger that are charged with an actual battery. The conventional charger topology is used either as a Buck converter or a Boost converter alone, which has the disadvantage that the battery can not always be charged to the desired maximum power as input and output conditions change. Although studies using a topology capable of boosting and stepping have been carried out, Buck-Boost converters or Sepic converters with relatively low efficiency have been used. In this paper, we propose a new Buck Boost combination power converter topology structure that can use Buck converter and Boost converter at the same time to improve inductor current ripple and power converter efficiency caused by wide voltage control range like solar charger.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1429-1439
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• 2019

Buck-Boost LLC (BBLLC) converters based on a PWM + phase control strategy are good candidates for high efficiency, high power density and wide input range applications. Nevertheless, they suffer from large computational complexity when it comes to calculating the optimal phase for ZVS of all the switches. In this paper, a method is proposed for a microcontroller unit (MCU) to calculate the optimal phase quickly and accurately. Firstly, a 2-D lookup table of the phase is established with an index of the input voltage and output current. Then, a bilinear interpolation method is applied to improve the accuracy. Meanwhile, simplification of the phase equation is presented to reduce the computational complexity. When compared with conventional curve-fitting and LUT methods, the proposed method makes the best tradeoff among the accuracy of the optimal phase, the computation time and the memory consumption of the MCU. Finally, A 350V-420V input, 24V/30A output experimental prototype is built to verify the proposed method. The efficiency can be improved by 1% when compared with the LUT method, and the computation time can be reduced by 13.5% when compared with the curve-fitting method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.95-103
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• 2011

This paper proposes a 6b 1.2 GS/s 47.8 mW 0.17 $mm^2$ 65 nm CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 $V_{p-p}$ at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 nm CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 dB and a maximum SFDR of 44.7 dB at 1.2 GS/s. The ADC with an active die area of 0.17 $mm^2$ consumes 47.8 mW at 1.2 V and 1.2 GS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.81-88
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• 2006

This paper describes a new linear operational transconductance amplifier (OTA). To improve the linearity of the OTA, we employ a mobility compensation circuit that combines the transistor paths operating at the triode and subthreshold regions. The common-mode control schemes consist of a common-mode feedback (CMFB) and common-mode feedforward (CMFF). The circuit enhances linearity of the transconductance (Gm) under the wide input voltage swing range. The proposed OTA shows ${\pm}1%$ Gm variation and the total harmonic distortion (THD) of below -73dB under the input voltage swing range of ${\pm}1.1V$. The OTA is implemented using a $0.35{\mu}m$ n-well CMOS process under 3.3V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.101-106
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• 2014

This paper presents a wide dynamic range radio-frequency (RF) root-mean-square (RMS) power detector using an automatic gain control (AGC) loop. The AGC loop consists of a variable gain amplifier (VGA), RMS conversion block and gain control block. The VGA exploits dB-linear gain characteristic of the cascade VGA. The proposed circuit utilizes full-wave squaring and generates a DC voltage proportional to the RMS of an input RF signal. The proposed RMS power detector operates from 500MHz to 5GHz. The detecting input signal range is from 0 dBm to -70 dBm or more with a conversion gain of -4.53 mV/dBm. The proposed RMS power detector is designed in a 65-nm 1.2-V CMOS process, and dissipates a power of 5 mW. The total active area is $0.0097mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.4
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• pp.20-30
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• 2001

A novel 200 MHz CMOS transconductor using translinear cells is proposed. The proposed transconductor consists of voltage followers and current followers based on translinear cells and a resistor. For wide applications, a single-input single-output, a single-Input differential-output, and a fully-differential transconductor are systematically designed, respectively. The theory of operation is described and computer simulation results are used to verify theoretical predictions. The results show that the fully-differential transconductor has a linear input voltage range of ${\pm}2.7$ V, a 3 dB frequency of 200 MHz, and a temperature coefficient of less than 41 $ppm/^{\circ}C$ at supply voltages of ${\pm}3$ V. In order to certify the applicability of the fully-differential transconductor, A ladder-type 3th-order cllitic low pass filter is also designed based on the inductance simulation method. The filter has a ripple bandwidth of 22 MHz, a pass-band ripple of 0.36 dB, and a cutoff frequency of 26 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.