• Journal of Biomedical Engineering Research
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• v.25 no.5
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• pp.335-342
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• 2004

This paper describes a trans-admittance scanner for breast cancer detection. A FPGA-based sinusoidal waveform generator produces a constant voltage. The voltage is applied between a hand-held electrode and a scan probe placed on the breast. The scan probe contains an 8x8 array of electrodes that are kept at the ground potential. Multi-channel precision digital ammeters using the phase-sensitive demodulation technique were developed to measure the exit current from each electrode in the array. Different regions of the breast are scanned by moving the probe on the breast. We could get trans-admittance images of resistor and saline phantoms with an anomaly inside. The images provided the information on the depth and location of the anomaly. In future studies, we need to improve the accuracy through a better calibration method. We plan to test the scanner's ability to detect a cancer lesion inside the human breast.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.