• Journal of the Korean Society for Railway
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• v.10 no.6
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• pp.730-734
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• 2007

In this paper, we suggest the criticality of Hidden Failure with regard to the design of watch dog timer, used to detect HALT on railway signaling embedded controller, via FMEA and FTA. Hidden Failure means reliability and safety degradation of the system due to any failure occurred on elements added for fault tolerance. In this paper, therefore, we design vital watch dog timer to prevent the system from operating in low SIL conditions and assess the safety of circuit on failure occurrence to demonstrate that safety degradation problems owing to existing design are supplemented.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1351-1361
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• 1999

The wide spread of multimedia system demands a large area viewing display device which can inform a message to many people in open area. This paper is about the design of a large area viewing LED panel control system. The control system runs on 16 bit microprocessor MC68EC000 and has following functions: 16 line clock and time, 2 channel priority interrupt, 2 channel direct memory access, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16 byte FIFO, IBM PC/AT compatible keyboard interface, ISA bus, battery backuped real time clock, battery backuped 256 byte SRAM and watch dog timer. The core circuits are implemented to ASIC, considering lower cost, higher reliability, higher performance, smaller dimension, and lower power consumption. This is verified by simulation and fabricated in 0.6 um CMOS SOG processes. The total gate count is 39,083 and the clock frequency is 48 MGz. The fabricated ASIC is mounted on test board.

• Proceedings of the KSRS Conference
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• 2003.11a
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• pp.1096-1098
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• 2003

SBC(Single Board Computer) is being developed for MSC(Multi-Spectral Camera) on KOMPSAT-2(Korea Multi-Purpose Satellite). SBC controls all the units of MSC system and gets commands and sends telemetry to and from spacecraft bus via 1553 communication channel. Due to the fact that SBC does very important roles for MSC system operation and SBC operates with 100% duty cycle, SBC is designed to have high reliability. SBC which has Intel 80486 as a main processor includes eight serial communication channels, one mil-std-1553 interface channel and several discrete interfaces. SBC incorporates 2Mbyte radiation hardened SRAM(Static Random Access Memory) and 1Mbyte flash memory. There are also PIC(Programmable Interrupt Controller), counter, WDT(Watch Dog Timer) in the SBC. In this paper, the design result of the SBC is presented.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.3
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• pp.137-143
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• 2017

This paper presents a smart parking guidance system based on IoT car-stoppers. The car-stopper embedding an IoT sensor module has the advantage of easy installation compared to conventional parking sensors buried in ground. The parking status data are transferred to the IoT gateway by the sequential point-to-point communication between the car-stoppers. The data transferred from the IoT gateway are stored in the web server, and parking spaces can be monitored remotely through the Android app in a smart device. An active/sleep cycle method using a watch dog timer is employed to reduce the power consumption of the battery powered car-stopper. The power consumption of the car-stopper is measured to be 80 and 25 mW at the active and sleep mode, respectively. A configuration of ultra-low-power IoT sensor module is proposed to minimize the power consumption in the sleep mode. The operation of the implemented system has been verified in a real-world parking lot.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.