• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.135-142
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• 2024

Cu-Cu bonding, one of the key technologies in advanced packaging, enhances semiconductor chip performance, miniaturization, and energy efficiency by facilitating rapid data transfer and low power consumption. However, the quality of the interface bonding can significantly impact overall bond quality, necessitating strategies to quickly detect and classify in-process defects. This study presents a methodology for detecting defects in wafer junction areas from Scanning Acoustic Microscopy images using a ResNet-50 based deep learning model. Additionally, the use of the defect map is proposed to rapidly inspect and categorize defects occurring during the Cu-Cu bonding process, thereby improving yield and productivity in semiconductor manufacturing.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1083-1086
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• 2005

Light scattering measurement system that can evaluate light scattering characteristic from defects on silicon wafer surface has been developed. The system uses $Ar^+$ laser as an illumination source, and a highly sensitive photomultiplier tube (PMT) for detecting scattered light from defects. Unlike with conventional measurement system, our system has ability to measure scattered light pattern from wide range of scattering angles with changeable incidence condition. It is shown that our developed system is effective to discriminate the types and sizes of defects from basic experimental results using a microscatch and a PSL sphere.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.314-314
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• 2012

The dilute magnetic semiconductors (DMS) have been developed to multi-functional electro-magnetic devices. Specially, the Si based DMS formed by ion implantation have strong advantages to improve magnetic properties because of the controllable effects of carrier concentration on ferromagnetism. In this study, we investigated the deep level states of Fe- and Co-ions implanted Si wafer during rapid thermal annealing (RTA) process. The p-type Si (100) wafers with hole concentration of $1{\times}10^{16}cm^{-3}$ were uniformly implanted by Fe and Co ions at a dose of $1{\times}10^{16}cm^{-2}$ with an energy of 60 keV. After RTA process at temperature ranges of $500{\sim}900^{\circ}C$ for 5 min in nitrogen ambient, the Au electrodes with thickness of 100 nm were deposited to fabricate a Schottky contact by thermal evaporator. The surface morphology, the crystal structure, and the defect state for Fe- and Co- ion implanted p-type Si wafers were investigated by an atomic force microscopy, a x-ray diffraction, and a deep level transient spectroscopy, respectively. Finally, we will discuss the physical relationship between the electrical properties and the variation of defect states for Fe- and Co-ions implanted Si wafer after RTA.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.88-89
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• 2009

In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.551-552
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• 2012

• Journal of the Microelectronics and Packaging Society
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• v.17 no.2
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• pp.29-33
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• 2010

Among several critical topics in semiconductor fabrication technology, particles in addition to bonded surface contaminations are issues of great concerns. This study reports the development of a system which inspects wafer bond integrity by analyzing laser beam transmittance deviations and the variations of the intensity caused by the defect thickness. Since the speckling phenomenon exists inherently as long as the laser is used as an optical source and it degrades the inspection accuracy, speckle contrast is another obstacle to be conquered in this system. Consequently speckle contrast reduction methods were reviewed and among the all remedies have been established in the past 30 years the most adaptable solution for inline inspection system is applied. Simulation and subsequently design of experiments has been utilized to discover the best solution to improve irradiance distribution and detection accuracy. Comparison between simulation and experimental results has been done and it confirms an outstanding detection accuracy achievement. Bonded wafer inspection system has been developed and it is ready to be implemented in FAB in the near future.

• Journal of the Korea Society of Computer and Information
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• v.14 no.10
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• pp.55-61
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• 2009

This paper describes a point of production(POP) system which collects and manages real-time shop floor machining information in a wafer dicing process. The system are composed of POP terminal, line controller and network. In the configuration of the system, LAN and RS485 network are used for connection with the upper management system and down stratum respectively. As a bridge between POP terminal and server, a line controller is used. The real-time information which is the base of production management are collected from information resources such as machine, product and worker. The collected information are used for the calculation of optimal cutting condition. The collection of the information includes cutting speed, spout of pure water, accumulated count of cut in process for blade and wafer defect. In order to manage machining information in wafer dicing process, production planning information is delivered to the shop floor, and production result information is collected from the shop floor, delivered to the server and used for managing production plan. From the result of the system application, production progress status, work and non-working hour analysis for each machine, and wafer defect analysis are available, and they are used for quality and productivity improvements in wafer dicing process. A case study is implemented to evaluate the performance of the system.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.2
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• pp.157-161
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• 1999

We investigated the effect of mechanical back side damage in Czochralski silicon wafer. The intensity of mechanical damage was evaluated by minority carrier recombination lifetime by laser excitation/microwave reflection photoconductance decay ($\mu$-PCD) technique, wet oxidation/preferential etching methods, near surface micro defect (NSMD) analysis, and X-ray section topography. The data indicate that the higher the mechanical damage intensity, the lower the minority carrier lifetime, and NSMD density increased proportionally, also correlated to the oxidation induced stacking fault (OISF) density. Thus, NSMD technique can be used separately from conventional etching method in OISF measurement.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.103.1-103.1
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• 2011

실리콘 이종접합 태양전지에서 계면 결함 밀도는 효율을 결정하는데 가장 중요한 요인으로 작용한다. 계면 결함은 캐리어의 재결합 위치로 작용하여, 계면 결함 밀도가 증가하면 재결합 속도가 증가하게 된다. 흡수층으로 사용되는 실리콘 웨이퍼 (결정질 실리콘)를 가능한 깨끗하게 세정함으로써, 또한 emitter로 쓰이는 비정질 실리콘을 낮은 데미지로 증착하여 계면 결함 밀도를 감소 시킬 수 있다. 이러한 계면 결함 밀도의 감소가 어떠한 변화로 인해 태양전지 특성에 영향을 주는지 시물레이션을 통해 알아보았다. n-type 웨이퍼에 p-type 비정질 실리콘을 emitter로 하여 TCO/p/i/n-type wafer/i/n/TCO/metal의 구조를 적용했고, wafer 전면과 i로 쓰인 무첨가된 비정질 실리콘 간의 계면 결함 밀도를 변수로 적용했다. 그 결과, 계면 결함 밀도가 감소함에 따라 재결합이 감소하여 태양전지 특성이 증가하는 측면도 있지만, 흡수층의 장벽 (barrier height)이 높아져 재결합을 더욱 감소시킴으로 인해 태양전지 특성이 증가함을 알 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.557-561
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• 2001

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integraded circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding 1㎛ in size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particles agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectrics(IMD)-CMP process. The filter installation in CMP polisher could reduce defects after IMD-CMP process. As a result of micro-scratch formation, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. We have concluded that slurry filter lifetime is fixed by the degree of generating defects.