• Title/Summary/Keyword: Wafer Cleaning

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마그네트론 스퍼터링을 이용한 Al과 Al-Si 박막의 제조 및 특성

  • Park, Hye-Seon;Jeong, Jae-In;Yang, Ji-Hun;Jeong, Jae-Hun;Song, Min-A
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.08a
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    • pp.309-309
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    • 2011
  • 알루미늄 합금은 경량성과 우수한 가공성, 내식성 등의 특성을 지니고 있고 구리나 아연, 마그네슘, 실리콘 등과 쉽게 합금화 가능하다. 또한 알루미늄과 그 합금은 자동차, 항공기, 건축물, 레저 그리고 가전용품의 재료로도 널리 사용되고 있다. 특히 Al에 Si을 소량 첨가하게 되면 내식성과 반사율이 향상되는 것으로 알려져 있다. 본 연구에서는 마그네트론 스퍼터링으로 Al, Al-Si 박막을 코팅하여 박막의 미세구조와 가시광선의 반사율을 관찰하였다. 시편은 Si wafer를 사용하였으며 알코올과 아세톤으로 각각 10분간 초음파 세척한 후 진공장비에 장착하여 Ar 분위기에서 glow discharge로 in-situ cleaning을 약 30분간 실시하였다. 시편청정이 끝나면 ~10-6 Torr 까지 진공배기를 실시하고 Ar 가스를 주입하여 2.5 mTorr로 진공도를 유지하면서 박막 코팅을 실시하였다. 기판-타겟의 거리는 12 cm로 고정 하였고 0.7, 1.5, 2.0 kW의 스퍼터링 파워와 외부 자기장의 변화에 따라 실험을 실시하였다. 순수한 Al 박막의 경우 외부 자기장 변화가 박막조직 변화에 영향을 주었으나 Si이 함유된 Al 합금 박막에서는 외부 자기장의 효과보다는 스퍼터링 전원의 세기가 박막 조직을 변화시키는 주된 공정변수였다. 박막의 반사율은 Si이 함유된 박막이 순수한 Al 박막보다 높았으며 스퍼터링 전원 세기가 증가할수록 반사율이 증가하는 경향성을 보였다. 이것은 Si을 Al에 첨가하여 스퍼터링 전원 세기를 최적화하는 것만으로도 치밀한 조직의 박막을 코팅할 수 있으며 높은 반사율을 갖는 박막을 코팅할 수 있음을 의미한다.

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Application of ultra pure water in semiconductor wet cleaning process (반도체 세정 공정에서의 초순수)

  • 송재인;박흥수;고영범;이문용
    • Proceedings of the Membrane Society of Korea Conference
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    • 1996.06a
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    • pp.149-153
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    • 1996
  • 반도체 소자 제조 공정이 고 집적화 됨에 따라 습식 세정방법에 의한 세정공정의 중요성이 더욱 증가 되어지고 있으며, 특히 그 중에서 전체 세정공정의 약 절반을 차지하고 있는 Deionised water에 의한 rinsing 공정의 경우 ultrapure water의 quality가 최근 지속적으로 향상이 되어짐에 따라 많은 발전을 자져 왔다. 일반적으로 Deionised water에 함유하고 있는 TOC(total oxidisable components), bacteria, metallic impurity, desolved oxygen cencentration, colloidal material impurity (예를 들면 Silica, oraganic substrate)등은 ultra pure water의 quality를 결정하는데 매우 중요한 factor로 작용하고 있으며, 이러한 불순물들이 반도체 제조공정중 wafer surface에 흡착되어 졌을때 여러형태의 defect들을 유발한다고 알려져 있다. 그러나 pseudommonas, flavobacterlum, alcaligene등의 기 얄려진 bacteria들의 경우 Deionised water를 supply해주는 배관의 Inner surface에 잘 흡착 되지만 고온의 water 혹은 과산화수소수($H_{2}O_{2}$) 를 이용하여 주기적으로 처리 해줌으로 인하여 이에 대한 문제점을 어느정도 최소화 시킬수 있다. 위의 두가지 방법중 전자의 경우 chemical을 사용하지 않고, 유지 및 관리가 간편하며, 용존산소량을 줄일수 있다는 점에서 장점이 있으나, 전 ultra pure water의 system이 열적으로 안정해야 하고 경제적인 문제가 수반하는 단점을 가지고 있다. 후자의 경우, 미량의 과산화수소수 (1~10,000 ppm)를 이용해 처리 해주는 방법의 경우 경제적으로 큰 장점이 있고, 처리가 단순하다는 장점이 있으나 과산화수소수 자체에 포함하고 있는 높은 impurit level, 그리고 처리후 장시간의 flushing time을 가져야 한다는 단점등이 존재 하고 있다.

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Reactive Ion Etching을 이용한 PTFE 발수특성

  • Baek, Cheol-Heum;Seo, Seong-Bo;;Kim, Hwa-Min
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.292-292
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    • 2013
  • 최근, 자연의 기능성 표면을 모사하여 우리 생활에 응용하기 위한 연구가 활발하다. 초-발수 특성을 가지는 대표적인 예인 연꽃잎은 마이크로-나노 크기의 거친 미세돌기(papillae)를 가지고 있으며 그 위에 낮은 표면 에너지를 가지는 왁스(wax)가 발달 되어 항상 깨끗한 상태를 유지한다. 본 실험에서는 이를 모사하여 RIE (Reactive Ion Etching)방법을 이용하여 기판인 Poly silicon wafer를 Sf6가스를 사용하여 Metal mash로 거칠기를 만들어 주었고, RF-magnetron sputtering 장치를 사용하여 $6{\times}10^{-3}$ Torr의 진공도에서 낮은 표면에너지를 가지는 PTFE (polytetrafluoroethylene)를 증착하여 표면 구조와 발수특성에 대하여 조사하였다. SSME(Surface shape measurement equipment)측정결과 0.24~0.36 um RSa 값이 측정되었고, 12 uL의 Di-water로 접촉각을 측정 한 결과 RIE 10분 처리를 한 기판 위에 PTFE를 3분 증착하였을 때 가장 높은 $153^{\circ}$의 초-발수 특성이 나타났으며, 4주의 시간이 지났을 때에도 접촉각이 유지가 되었다. XPS 측정결과 초-발수 표면에서 나타나는 CF2와 CF3 피크 값이 측정되었다. Reactive Ion Etching을 이용한 PTFE 발수 특성은 방수, 스마트 윈도우, 자가세정(Self-Cleaning), 디스플레이 표시장치, 김서림 방지(Anti-Fogging), 대전방지 코팅 등에 다각적으로 응용 가능할 것이라 사료된다.

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CMP Slurry Induction Properties of Silicate Oxides Deposited on Silicon Wafer (실리콘 웨이퍼위에 증착된 실리케이트 산화막의 CMP 슬러리 오염 특성)

  • 김상용;서용진;이우선;장의구
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.2
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    • pp.131-136
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    • 2000
  • We have investigated the slurry induced metallic contaminations of undoped and doped silicate oxides surface on CMP cleaning process. The metallic contaminations by CMP slurry were evaluated in four different oxide films, such as plasma enhanced tetra-ethyl-orthyo-silicate glass(PE-TEOS), O3 boro-phos-pho-silicate glass(O3-BPSG), PE-BPSG, and phospho-silicate glass(PSG). All films were polished with KOH-based slurry prior to entering the post-CMP cleaner. The Total X-Ray fluorescence(TXRF) measurements showed that all oxide surfaces are heavily contaminated by potassium and calcium during polishing which is due to a CMP slurry. The polished O3-BPSG films presented higher potassium and calcium contaminations compared to PE-TEOS because of a mobile ions gettering ability of phosphorus. For PSG oxides, the slurry induced mobile ion contamination increased with an increase of phosphorus contents. In addition, the polishing removal rate of PSG oxides had a linear relationship as a function of phosphorus contents.

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Direct Bonding of Si II 1.3$\mu\textrm{m}$-SiO$_2$/1.3$\mu\textrm{m}$-SiO$_2$ II SOI substrates prepared by FLA method (선형접합기를 이용한 Si II 1.3$\mu\textrm{m}$-SiO$_2$/1.3$\mu\textrm{m}$-SiO$_2$ II SOI 기판의 직접접합)

  • 송오성;이영민;이상현;이진우;강춘식
    • Journal of the Korean institute of surface engineering
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    • v.34 no.1
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    • pp.33-38
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    • 2001
  • 10cm-diameter Si(100)∥$1.3\mu\textrm{m}$-X$1.3_2$X$1.3\mu\textrm{m}$-$SiO_2$∥Si(100) afers were prepared using a fast linear annealing (FLA) equipment. 1.3$\mu\textrm{m}$-thick $SiO_2$ films were grown by dry oxidation process. After cleaning and premating the wafers in a class 100 clean room, they were heat treated using with the FLA and conventional electric furnace. Bonded area and bond strength of wafer pairs were measured using a infrared (IR) camera and razor blade crack opening method, respectively. It was confinmed that the bonded area by FLA was around 99% and the bond strength value reached 2172mJ/$\m^2$, which is equivalent to theoritical bond strength. Our result implies that thick $SiO_2$ SOI may be prepared more easily by using $SiO_2$$SiO_2$ bonding interfaces then those of Si/$SiO_2$'s.

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The Cu-CMP's features regarding the additional volume of oxidizer (산화제 배합비에 따른 연마입자 크기와 Cu-CMP의 특성)

  • Kim, Tae-Wan;Lee, Woo-Sun;Choi, Gwon-Woo;Seo, Young-Jin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.20-23
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    • 2004
  • As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

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Influence of KOH Solution on the Passivation of Al2O3 Grown by Atomic Layer Depostion on Silicon Solar Cell

  • Jo, Yeong-Jun;Jang, Hyo-Sik
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.299.2-299.2
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    • 2013
  • We investigated the potassium remaining on a crystalline silicon solar cell after potassium hydroxide (KOH) etching and its effect on the lifetime of the solar cell. KOH etching is generally used to remove the saw damage caused by cutting a Si ingot; it can also be used to etch the rear side of a textured crystalline silicon solar cell before atomic layer-deposited Al2O3 growth. However, the potassium remaining after KOH etching is known to be detrimental to the efficiency of Si solar cells. In this study, we etched a crystalline silicon solar cell in three ways in order to determine the effect of the potassium remnant on the efficiency of Si solar cells. After KOH etching, KOH and tetramethylammonium hydroxide (TMAH) were used to etch the rear side of a crystalline silicon solar cell. To passivate the rear side, an Al2O3 layer was deposited by atomic layer deposition (ALD). After ALD Al2O3 growth on the KOH-etched Si surface, we measured the lifetime of the solar cell by quasi steady-state photoconductance (QSSPC, Sinton WCT-120) to analyze how effectively the Al2O3 layer passivated the interface of the Al2O3 layer and the Si surface. Secondary ion mass spectroscopy (SIMS) was also used to measure how much potassium remained on the surface of the Si wafer and at the interface of the Al2O3 layer and the Si surface after KOH etching and wet cleaning.

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VOID DEFECTS IN COBALT-DISILICIDE FOR LOGIC DEVICES

  • Song, Ohsung;Ahn, Youngsook
    • Journal of the Korean institute of surface engineering
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    • v.32 no.3
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    • pp.389-392
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    • 1999
  • We employed cobalt-disilicide for high-speed logic devices. We prepared stable and low resistant $CoSi_2$ through typical fabrication process including wet cleaning and rapid thermal process (RTP). We sputtered 15nm thick cobalt on the wafer and performed RTP annealing 2 times to obtain 60nm thick $CoSi_2$. We observed spherical shape voids with diameter of 40nm in the surface and inside $CoSi_2$ layers. The voids resulted in taking over abnormal junction leakage current and contact resistance values. We report that the voids in $CoSi_2$ layers are resulted from surface pits during the ion implantation previous to deposit cobalt layer. Silicide reaction rate around pits was enhanced due to Gibbs-Thompson effects and the volume expansion of the silicidation of the flat active regime trapped dimples. We confirmed that keeping the buffer oxide layer during ion implantation and annealing the silicon surface after ion implantation were required to prevent void defects in CoSi$_2$ layers.

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Effect of Citric Acid in Cu Chemical Mechanical Planarization Slurry on Frictional Characteristics and Step Height Reduction of Cu Pattern

  • Lee, Hyunseop
    • Tribology and Lubricants
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    • v.34 no.6
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    • pp.226-234
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    • 2018
  • Copper chemical mechanical planarization (CMP) has become a key process in integrated circuit (IC) technology. The results of copper CMP depend not only on the mechanical abrasion, but also on the slurry chemistry. The slurry used for Cu CMP is known to have greater chemical reactivity than mechanical material removal. The Cu CMP slurry is composed of abrasive particles, an oxidizing agent, a complexing agent, and a corrosion inhibitor. Citric acid can be used as the complexing agent in Cu CMP slurries, and is widely used for post-CMP cleaning. Although many studies have investigated the effect of citric acid on Cu CMP, no studies have yet been conducted on the interfacial friction characteristics and step height reduction in CMP patterns. In this study, the effect of citric acid on the friction characteristics and step height reduction in a copper wafer with varying pattern densities during CMP are investigated. The prepared slurry consists of citric acid ($C_6H_8O_7$), hydrogen peroxide ($H_2O_2$), and colloidal silica. The friction force is found to depend on the concentration of citric acid in the copper CMP slurry. The step heights of the patterns decrease rapidly with decreasing citric acid concentration in the copper CMP slurry. The step height of the copper pattern decreases more slowly in high-density regions than in low-density regions.

Study on the Fabrication of Tunnel Type $E^2PROM$ and Its Characteristics (터널링형 $E^2PROM$ 제작 및 그 특성에 관한 연구)

  • Kim, Jong Dae;Kim, Sung Ihl;Kim, Bo Woo;Lee, Jin Hyo
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.1
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    • pp.65-73
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    • 1986
  • Experiment have been conducted about thin oxide characteristics according to O2/N2 ratio needed for EEPROM cell fabrication. As a result, we think that there is no problem even if we grow oxide layer with large O2/N2 ratio and short exidation time and when the water is implated by As before oxidation, the oxide breakdown field is about IMV/cm lower than that is not implanted. Especially, the thin oxide characteristic seems to be affected largely by wafer cleaning and oxidation in air. On the basis of these, tunnel type EEPROM cell is fabricated by 3um CMOS process and its characteristic is studied. Tunnel oxide thickness(100\ulcorner is chosen to allow Fowler-Nordheim tunneling to charge the floating gate at the desired programming voltage and tunnel area(2x2um\ulcorneris chosen to increase capacitive coupling ratio. For program operation, high voltage (20-22V) is applied to the control gate, while both drain and source are gdrounded. The drain voltage for erase is 16V. It is shown that charge retention characteristics is not limited by leakage in the oxide and program/erase endurance is over 10E4 cycles of program erase operation.

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