• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1305-1306
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• 2007

To lower the fabrication cost of silicon solar cells, a surface treatment using a dielectric barrier discharge instead of a wet cleaning technique was examined on electrode surfaces on silicon solar cells. The fill factor obtained through measuring current-voltage characteristics was evaluated, and the treated surface state was characterized by energy-dispersive X-ray. It was found that the dielectric barrier discharge effectively activated the electrode surface and the surface treatment on finger electrodes contributed greatly to improve the fill factor.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.6
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• pp.32-38
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• 2010

Laser material processing technology is adopted in several industry as alternative process which could overcome weakness and problems of present adopted process, especially semiconductor and display industry. In semiconductor industry, laser photo lithography is doing at front-end level, and cutting, drilling, and marking technology for both wafer and EMC mold package is adopted. Laser cleaning and de-flashing are new rising technology. There are 3 kinds of main display industry which use laser technology - TFT LCD, AMOLED, Touch screen. Laser glass cutting, laser marking, laser direct patterning, laser annealing, laser repairing, laser frit sealing are major application in display industry.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.330-333
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• 2005

The fabrication of mold fur nano imprint lithography (NIL) is experimentally reported using the scanning probe lithography (SPL) technique, instead of the conventional I-beam lithography technique. The nanometer scale patterning structure is fabricated by the localized generation of oxide patterning on the silicon (100) wafer surface with a thin oxide layer, The fabrication method is based on the contact mode of scanning probe microscope (SPM) in air, The precision cleaning process is also performed to reach the low roughness value of $R_{rms}=0.084 nm$, which is important to increase the reproducibility of patterning. The height and width of the oxide dot are generated to be 15.667 nm and 209.5 nm, respectively, by applying 17 V during 350 ms.

• Tribology and Lubricants
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• v.35 no.5
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• pp.274-285
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• 2019

Chemical mechanical polishing (CMP), which is a material removal process involving chemical surface reactions and mechanical abrasive action, is an essential manufacturing process for obtaining high-quality semiconductor surfaces with ultrahigh precision features. Recent rapid growth in the industries of digital devices and semiconductors has accelerated the demands for processing of various substrate and film materials. In addition, to solve many issues and challenges related to high integration such as micro-defects, non-uniformity, and post-process cleaning, it has become increasingly necessary to approach and understand the processing mechanisms for various substrate materials and abrasive particle behaviors from a tribological point of view. Based on these backgrounds, we review recent CMP R&D trends in this study. We examine experimental and analytical studies with a focus on substrate materials and abrasive particles. For the reduction of micro-scratch generation, understanding the correlation between friction and the generation mechanism by abrasive particle behaviors is critical. Furthermore, the contact stiffness at the wafer-particle (slurry)-pad interface should be carefully considered. Regarding substrate materials, recent research trends and technologies have been introduced that focus on sapphire (${\alpha}$-alumina, $Al_2O_3$), silicon carbide (SiC), and gallium nitride (GaN), which are used for organic light emitting devices. High-speed processing technology that does not generate surface defects should be developed for low-cost production of various substrates. For this purpose, effective methods for reducing and removing surface residues and deformed layers should be explored through tribological approaches. Finally, we present future challenges and issues related to the CMP process from a tribological perspective.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.6
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• pp.425-428
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• 2013

In this paper, we present a novel hydrophilic coating material (Wellture Finetech, Korea) which can be utilized as a coating layer for anti-contamination for electrical and electronic system. The coating material was deposited on 4 inch silicon wafer with several different film thickness. The film thickness was controlled by spin coating speed. After curing of the film, we have scratched by permanent marker to check self-cleaning property of the film. Also we have executed several mechanical tests of the films. As the spin coating speed is increased, the film thickness was thinned from 230 nm to 125 nm. Contact angle of the film was lowered from $30^{\circ}$ to $12^{\circ}$ as the spin coating speed is increased from 700 to 2,500 rpm. On permanent marker scratched film surface coated at 1,000 rpm, we have poured regular city water to investigate self cleaning property of the film. The scratches were gradually separated from the film surface due to super-hydrophilicity of the film. Hardness of spin coated film was 9H measured by ASTM D3363 method. and adhesion of all film was 5B tested by ASTM D3359 method. Also, to get exact hardness value of the film, we have utilized a nano-indenter. As spin speed is increased, the hardness of film was increased from 3 GPa to 5 GPa.

• Korean Chemical Engineering Research
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• v.51 no.6
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• pp.666-670
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• 2013

Recovery method of silicon wafer from defective products generated from manufacturing process of silicon solar cells was studied. The removal effect of the N layer and antireflection coating (ARC) of the waste solar cell were investigated at room temperature ($25^{\circ}C$) by variation of concentration of $H_3PO_4$, $NH_4HF_2$, and concentration and types of chelating agent. Removal efficiency was the best in the conditions; 10 wt% $H_3PO_4$ 2.0 wt% $NH_4HF_2$, 1.5 wt% Hydantoin. Increasing the concentration of $H_3PO_4$, the surface contamination degree was increased and the thickness of the silicon wafe became thicker than the thickness before surface treatment because of re-adsorption on the silicon wafer surface by electrostatic attraction of the fine particles changed to (+). The etching method by mixed solution of $H_3PO_4$-$NH_4HF_2$-chelating agents was expected to be great as an alternative to conventional RCA cleaning methods and as the recycle method of waste solar cells, because all processes are performed at room temperature, the process is simple, and less wastewater, the removal efficiency of the surface of the solar cell was excellent.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.9
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• pp.423-430
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• 2002

The fabrication and experimentation of multi-channel electrodes which enable detecting and recording of multi-site neuronal signals have been investigated. A multi-channel electrode array was fabricated by depositing 2000${\AA}$ thick Au layer on the 1000${\AA}$ thick Ti adhesion layer on a glass wafer. The metal paths were patterned by wet etching and passivated by depositing a PECVD silicon nitride insulation layer to prevent signals from intermixing or cross-talking. After placing a thin slice of rat cerebellar granule cell in the culture ring located in central portion of the multi-channel electrode plate, a neuronal signal from an electrode which is in contact with the cerebellar granule cell has been detected. It was found that the electrode impedance ranges 200㏀∼1㏁ and the impedance is not changed by cleaning with nitric acid. Also, the impedance is inversely proportion to the exposed electrode area and the cross-talk is negligible when the electrode spacing is bigger than 600$\mu\textrm{m}$. The amplitude and frequency of the measured action potential were 38㎷ and 2㎑, which are typical values. From the experimental results, the fabricated multi-channel electrode array proved to be suitable for multi-site neuronal signal detection for the analysis of a complicated cell network.

• Journal of the Korean institute of surface engineering
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• v.33 no.2
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• pp.101-106
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• 2000

SOI (Silicon-On-Insulator) substrates were fabricated with varying annealing temperature of $25-660^{\circ}C$ by a linear annealing method, which was modified RTA process using a linear shape heat source. The annealing method was applied to Si ∥ $SiO_2$/Si pair pre-contacted at room temperature after wet cleaning process. The bonding strength of SOI substrates was measured by two methods of Razor-blade crack opening and direct tensile test. The fractured surfaces after direct tensile test were also investigated by the optical microscope as well as $\alpha$-STEP gauge. The interface bonding energy was 1140mJ/m$^2$ at the annealing temperature of $430^{\circ}C$. The fracture strength was about 21MPa at the temperature of $430^{\circ}C$. These mechanical properties were not reported with the conventional furnace annealing or rapid thermal annealing method at the temperature below $500^{\circ}C$. Our results imply that the bonded wafer pair could endure CMP (Chemo-Mechanical Polishing) or Lapping process without debonding, fracture or dopant redistribution.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.1
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• pp.199-206
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• 2005

Mask manufacturing is a high COC and COO process in developing of semiconductor devices because of mask production tool with high resolution. Direct writing has been thought to be the one of the patterning method to cope with development or small-lot production of the device. This study consists two categories. One is the additional process of the direct and maskless patterning generation using SLA for easy and convenient application and the other is a removal process using wet-etching process. In this study, cured status of epoxy pattern is most important parameter because of the beer-lambert law according to the diffusion of UV light. In order to improve the contact force between patterns and substrate, prime process was performed and to remove the semi-cured resin which makes a bad effects to the pattern, spin cleaning process using TPM was also performed. At a removal process, contact force between photo-curable resin as an etching mask and Si wafer is important parameter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.370-373
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical Planarization(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper depostion is a mature process from a historical point of view, but a very young process from a CMP persperspective. While copper electrodepostion has been used and stuidied for dacades, its application to Cu damascene wafer processing is only now ganing complete accptance in the semiconductor industry. The polishing mechanism of Cu CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper pasivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.