• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.56-62
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• 2002

A new high speed and low voltage swing on-chip BUS using threshold voltage swing driver and dual sense amplifier receiver is proposed. The threshold voltage swing driver reduces the rising time in the bus to 30% of the full CMOS inverter driver and the dual sense amplifier receiver increases twice the throughput. of the conventional reduced-swing buses using sense amplifier receiver. With threshold voltage swing driver and dual sense amplifier receiver combined, approximately 60% speed improvement and 75% power reduction are achieved in the proposed scheme compared to the conventional full CMOS inverter for the on-chip bus.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.79-82
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• 2003

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to $V_{ref}-V_{TH}$, where $V_{ref}=V_{DD}-nV_{TH}$. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we propose a low-power $4\times4$ bit parallel multiplier. The proposed circuits are simulated with HSPICE under $0.35{\mu}m$ CMOS standard technology. Compare to the previous works, this circuit can reduce the power consumption rate of 11.2% and the power-delay product of 10.3%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.104-109
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• 2009

At a lower supply voltage, voltage-mode drivers draw less current than current-mode drivers. In this paper, we newly propose a voltage-mode driver with an additional current path that reduces the output voltage swing without the need for complicated additional circuitry, compared to conventional voltage-mode drivers. The prototype driver is fabriccated in a 0.13-$^{\mu}m$ CMOS technology and used to transmit data streams at the rate of 2.5 Gb/s. Deemphasis is also implemented for the compensation of channel attenuation. With a 1.2-V supply, it dissipates 8.0 mA for a 400-mV output voltage swing.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.147-150
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• 2007

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16$\times$16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35$\mu$m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.10-16
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• 1999

This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.401-406
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• 2015

The change of subthreshold swing for channel length of asymmetric double gate(DG) MOSFET has been analyzed. The subthreshold swing is the important factor to determine digital chracteristics of transistor and is degraded with reduction of channel. The subthreshold swing for channel length of the DGMOSFET developed to solve this problem is investigated for channel thickness, oxide thickness, top and bottom gate voltage and doping concentration. Especially the subthreshold swing for asymmetric DGMOSFET to be able to be fabricated with different top and bottom gate structure is investigated in detail for bottom gate voltage and bottom oxide thickness. To obtain the analytical subthreshold swing, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. As a result, subthreshold swing is sensitively changed according to top and bottom gate voltage, channel doping concentration and channel dimension.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.657-662
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• 2014

This paper has analyzed the subthreshold swings for top and bottom gate voltages of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates. The subthreshold swing, therefore, has to be analyze not only for top gate voltage, but also for bottom gate voltage. In the pursuit of this purpose, Poisson equation has been solved to obtain the analytical solution of potential distribution with Gaussian function, and the subthreshold swing model has been presented. As a result to observe the subthreshold swings for the change of top and bottom gate voltage using this subthreshold swing model, we know the subthreshold swings are greatly changed for gate voltages. Especially we know the conduction path has been changed for top and bottom gate voltage and this is expected to greatly influence on subthreshold swings.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.221-226
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• 2008

A new two dimensional (2-D) analytical model for the Threshold Voltage on dual material surrounding gate (DMSG) MOSFETs is presented in this paper. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expression for the threshold voltage and sub-threshold swing is derived. It is seen that short channel effects (SCEs) in this structure is suppressed because of the perceivable step in the surface potential which screens the drain potential. We demonstrate that the proposed model exhibits significantly reduced SCEs, thus make it a more reliable device configuration for high speed wireless communication than the conventional single material surrounding gate (SMSG) MOSFETs.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.525-526
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• 2008

This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.490-492
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• 2010

A swing level controlled voltage-mode transmitter is proposed to support a stub series-terminated logic channel with center-tapped termination. This transmitter provides a swing level control to support the diagnostic mode and improve the signal integrity in the absence of the destination termination. By using the variable parallel termination, the proposed transmitter maintains the constant output impedance of the source termination while the swing level is controlled. Also, the series termination using an external resistor is used to reduce the impedance mismatch effect due to the parasitic components of the capacitor and inductor. To verify the proposed transmitter, the voltage-mode driver, which provides eight swing levels with the constant output impedance of about $50{\Omega}$, was implemented using a 70nm 1-poly 3-metal DRAM process with a 1.5V supply. The jitter reduction of 54% was measured with the swing level controlled voltage-mode driver in the absence of the destination termination at 1.6-Gb/s.