• Journal of KIISE:Information Networking
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• v.35 no.3
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• pp.235-242
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• 2008

To improve video quality and coding efficiency, H.264/AVC adopted an adaptive rate control. But this method has a problem as it cannot predict an accurate quantization parameter(QP) for the first frame. The first QP is decided among four constant values by using encoder input parameters. It does not consider encoding bits, results in significant fluctuation of the image quality and decreases the average quality of the whole coded sequence. In this paper, we propose a new algorithm for the first frame QP decision in the H.264/AVC encoder. The QP is decided by the existing algorithm and the first frame is encoded. According to the encoded bits, the new initial QP is decided. We can predict optimal value because there is a linear relationship between encoded bits and the new initial QP. Next, we re-encode the first frame using the new initial QP. Experimental results show that the proposed algorithm not only achieves better quality than the state of the art algorithm, but also adopts a rate control forthe sequence that was impossible with the existing algorithm. By reducing fluctuation, subjective quality also improved.

• Journal of Broadcast Engineering
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• v.17 no.5
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• pp.716-724
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• 2012

In this paper, we propose a fast decision method of maximum coding depth decision and reference frame selection in HEVC. To reduce computational complexity and encoding time of HEVC, two methods are proposed. In the first method, the maximum depth of each coding unit (CU) in a largest CU (LCU) is constrained by using the maximum coding depth used by adjacent LCUs based on the assumption that the spatial correlation is very high and rate-distortion (R-D) cost. And we constrain the number of reference pictures for prediction unit (PU) performing motion estimation by using the motion information of the upper depth PU. The proposed methods reduce computational complexity of the HEVC encoder by constraining the maximum coding depth and the reference frame. We could achieve about 39% computational complexity reduction with marginal bitrate increase of 1.2% in the comparison with HM6.1 HEVC reference software.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.8-16
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• 2007

For the improvement of coding efficiency, the H.264/AVC video coding standard employs new coding tools compared with existing coding standards. However, due to these new coding tools, the complexity of K264/AVC standard encoder is greatly increased. Specifically, the inter/intra mode decision method using RDO(rate-distortion optimization) technique is one of the most complex parts in H.264/AVC. In this paper, we focus on the complexity reduction in macroblock mode decision. In the proposed method, we reduce the complexity of the $4{\times}4$ mode decision process using $4{\times}4$ simple square filters, and using spatial block correlation method. Additionally, exploiting the best mode of sub_macroblock in $Inter8{\times}8$ mode, we proposed an algorithm to eliminate some intra modes in current macroblock mode decision process. In addition, we employed a method to raise the probability to select SKIP, $Intra16{\times}16$, and $Intra16{\times}16$ modes which usually show low complexity and low bitrate compared with other modes. From the simulation results, the proposed algorithm reduce the encoding time by maximum 83% of total, and reduce the bitrate of the overall sequences by $8{\sim}10%$ on the average compared with existing coding methods.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.8
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• pp.15-22
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• 2019

Awireless sensor network utilizes small sensors with a low cost and low power being deployed over a wide area. They monitor the surrounding environment and gather the associated information to transmit it to a base station via multi-hop transmission. Most of the research has mainly focused on static sensors that are located in a fixed position. Unlike a wireless sensor network based on static sensors, we can exploit drone-based technologies for more efficient wireless networks in terms of coverage and energy. In this paper, we introduce a transmission power model and a video encoding power model to design the network environment. We also explain a priority mapping scheme, and deploy drones oriented for network coverage and energy consumption. Through our simulations, this research shows coverage and energy improvements in adrone-based wireless sensor network with fewer sensors, compared to astatic sensor-based wireless sensor network. Concretely, coverage increases by 30% for thedrone-based wireless sensor network with the same number of sensors. Moreover, we save an average of 25% with respect to the total energy consumption of the network while maintaining the coverage required.