• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.408-411
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• 2008

In an attempt to enhance luminance efficiency and to reduce discharge delays of test panels with aluminum fence-electrodes, various designs of the electrodes were prepared by chemically etching the aluminum foils bonded to soda-lime glass substrate via anodic bonding process. The effects of fence design on luminance and discharge characteristics were investigated and compared with conventional ac-PDPs. These results showed a possibility of using fence-type aluminum electrode at front plates of ac-PDDs without sacrificing its performance.

• Journal of the Korean Chemical Society
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• v.58 no.6
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• pp.524-527
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• 2014

We report a simple yet efficient method to assemble large-scale aligned graphene nanoribbons (GNRs) with a width as small as 30 nm. The $V_2O_5$ nanowires (NWs) were aligned on a graphene surface via spraying a solution of the $V_2O_5$ NWs, and the graphene was selectively etched by the reactive ion etching method using the $V_2O_5$ NWs as a shadow mask. This process allowed us to prepare large scale patterns of the aligned GNRs on a $SiO_2$ substrate. The orientation of the aligned and randomly oriented GNRs was compared by the atomic force microscope (AFM) images. We achieved the highly aligned GNRs along the flow direction of the $V_2O_5$ NWs solution. Furthermore, we successfully fabricated a field effect-transistor with the aligned GNRs and measured its electrical properties. Since our method enable to prepare the aligned GNRs over a large area, it should open up new way for the various applications.

• Journal of Information Display
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• v.10 no.2
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• pp.54-61
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• 2009

The results of the optimization of the organic passivation process for fabricating thin-film transistors (TFTs) with a high aperture ratio on a seventh-generation glass (2200${\times}$1870 mm) substrate for LCD-TV panels are reported herein. The optimization of the organic passivation process has been verified by checking various factors, including the material properties (e.g., thickness, stain, etching, thermal reflow) and the effects on the TFT operation (e.g., gate/data line delay and display-driving properties). The two main factors influencing the organic passivation process are the optimization of the final thickness of the organic passivation layer, and the gate electrode. In conclusion, the minimum possible final thickness was found to be $2.42{\um}m$ via simulation and pilot testing, using the full-factorial design. The optimization of the organic passivation layer was accomplished by improving its brightness by over 10 cd/$m^2$ (ca. 2% luminance) compared to that of the conventional organic passivation process. The results of this research also help reduce the reddish stain on display panels.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.247-247
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• 2009

3차원 반도체 패키징에서 관통전극 Through Silicon Via (TSV)를 형성하기 위하여 이온과 래디컬의 활성도 조절이 가능한 pulsating inductively coupled plasma (ICP) 식각을 수행하였다. 본 식각공정에서는 펄스주파수 ($50{\sim}500Hz$)와 듀티 싸이클 ($20{\sim}99%$)을 조절하여, 플라즈마 내 이온과 래디컬들의 활성도 변화를 발생시켰다. 플라즈마 공정변수에 따라 식각형태가 달라짐을 S.E.M을 이용하여 확인했으며, 이온(SFx+, O+)과 래디컬 ($SF^*$, $F^*$, $O^*$)의 농도 및 활성도 변화를 측정하기 위하여 광학적 기술인 optical emissin spectroscopy와 전기적 특성 측정 기술인 Langmuir probe 시스템을 직접 제작 설치하여 펄스플라즈마를 진단하였다.

• Bulletin of the Korean Chemical Society
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• v.33 no.1
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• pp.83-89
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• 2012

Due to the potential importance and usefulness, usage of highly ordered nanoporous anodized aluminum oxide can be broadened in industry, when highly ordered anodized aluminum oxide can be placed on a substrate with controlled thickness. Here we report a facile route to highly ordered nanoporous alumina with the thickness of hundreds-of-nanometer on a silicon wafer substrate. Hexagonally or tetragonally ordered nanoporous alumina could be prepared by way of thermal imprinting, dry etching, and anodization. Adoption of reusable polymer soft molds enabled the control of the thickness of the highly ordered porous alumina. It also increased reproducibility of imprinting process and reduced the expense for mold production and pattern generation. As nanoporous alumina templates are mechanically and thermally stable, we expect that the simple and costeffective fabrication through our method would be highly applicable in electronics industry.

• Journal of the Korean Ceramic Society
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• v.44 no.7
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• pp.358-361
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• 2007

Well-ordered mesoporous SiCBN ceramics have been successfully synthesized by infiltrating a polymeric precursor, which was prepared from borazine and 2,4,6-trimethyl-2,4,6-trivinylcyclotrisilazane via a hydroboration reaction, into a mesoporous carbon (CMK-3) as a hard template. This was followed by pyrolysis at $1400^{\circ}C$ under nitrogen gas and subsequent oxidative removal of the carbon template without chemical etching. The prepared mesoporous SiCBN ceramic was characterized by a small-angle XRD, TEM, and BET surface area. The resulting mesoporous SiCBN ceramic revealed a BET surface area of $275 m^2g^{-1}$ and a pore volume of $0.8 cm^3 g$ with no crystallization.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.5
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• pp.397-401
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• 2008

Most of the topic in PCB industry was about increasing the volume of product for the development of electronics in numerous industrial application area. However, it has been emerged that yield improvement quality manufacturing via detecting any suspicious process in order to minimize the scrapped product and material waste. In addition, recently, restriction of hazardous substances (RoHS) claims that electronic manufacturing environment should reduce the harmful chemicals usage, thus the importance of monitoring copper etchant and detecting any mis-processing is crucial for electronics manufacturing. In this paper, we have developed real-time chemical monitoring system using RGB sensor, which is simpler but more accurate method than commercially utilized oxidation reduction potential (ORP) technique. The developed Cu etchant monitoring system can further be utilized for copper interconnect process in future nano-semiconductor process.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.12-17
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• 2003

본 연구에서는 MICP Etching system 을 이용한 Via contact 및 Deep contact hole etch process 특성을 연구하였다. Langmuir probe 를 이용한 MICP source 의 Plasma density & electron temperature 측정하였고 탄소와 플로우르를 포함하는 혼합 Plasma 를 형성하여 RF frequency, wall temperature, chamber gap, gas chemistry 등의 변화에 따른 식각 특성을 조사하였다. Plasma density 는 1000w 에서 $10^{11}$/$cm^3$ 이상의 high density plasma와 uniform plasma 형성을 확인하였고 $CH_{2}F_{2}$와 CO의 적절한 혼합비를 이용하여 Oxide to PR 선택비가 10 이상인 고선택비 조건을 확보하였다. 고선택비 형성에 따라 Polymer 형성이 많이 되었고 이를 개선하기 위하여 반응 챔버의 온도 조절을 통하여 Polymer 증착 방지에 효과적인 것을 확인하였다. MICP source를 이용하여 탄소와 플로우르의 혼합 가스와 식각 챔버의 온도 조절에 의한 선택비 증가를 확보하여 High Aspect Ratio Contact Hole Etch 가능성을 확보하였다.

• Journal of the Korean institute of surface engineering
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• v.55 no.6
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• pp.328-341
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• 2022

Area selective atomic layer deposition (AS-ALD) is a bottom-up nanopattern fabrication method that can grow the ALD films only on the desired substrate areas without using photolithography and etching processes. Particularly, AS-ALD has attracted great attention in the semiconductor manufacturing process due to its advantage in reducing edge placement error by fabricating self-aligned patterns. In this paper, the basic principles and characteristics of AS-ALD are described. In addition, various approaches for achieving AS-ALD with excellent selectivity were comprehensively reviewed. Finally, the technology development to overcome the selectivity limit of AS-ALD was introduced along with future prospects.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.73-78
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• 2016

An increase in the transistor density of integrated circuit devices leads to a very high increase in heat dissipation density, which causes a long-term reliability and various thermal problems in microelectronics. In this study, liquid cooling method was investigated using straight microchannels with various metal bumps. Microchannels were fabricated on Si wafer using deep reactive ion etching (DRIE), and Ag, Cu, or Cr/Au/Cu metal bumps were placed on Si wafer by a screen printing method. The surface temperature of liquid cooling structures with various metal bumps was measured by infrared (IR) microscopy. For liquid cooling with Cr/Au/Cu bumps, the surface temperature difference before and after liquid cooling was $45.2^{\circ}C$ and the power density drop was $2.8W/cm^2$ at $200^{\circ}C$ heating temperature.