• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.155-162
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• 1989

In this paper, we propose a channel router for non-rectangular channels with variable channel height and via minimization method. Non-rectangular routing areas are splitted into 3 parts, upper, lower and rectangular channel. The upper and lower parts are routed by a modified "left edge algorithm." The rectangular channel is routed by channel routing method using the channel representation graph. After routing, redundant vias are eliminated by the rules composed of 3 groups.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.114-121
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• 2003

Through comparing stress state of TEOS and SiLK-embedded structures, the effect of low-k materials on stress and stress distribution in via-line structures were investigated using three-dimensional finite element analyses. In the case of TEOS-embedded via-line structures, hydrostatic stress was concentrated at the via and the top of the lines, where the void was suspected to nucleate. On the other hand, in the via-line structures integrated with SiLK, large von-Mises stress is maintained at the via, thus deformation of via is expected as the main failure mode. A good correlation between the calculated results and experimentally observed failure modes according to dielectric materials was obtained.

• Journal of the Korea Computer Industry Society
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• v.2 no.9
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• pp.1239-1244
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• 2001

The Virtual Interface Architecture (VIA) is usually suggested as a new standard high-performance communication of the cluster systems. However the VIA specification aims for platform independence, the current Intel VI Provider Library (VIPL) design favors systems with Intel architecture processors running the Windows operating system (OS). This paper aims for clarifying the guesstion problem of VIA and VIPL in the newtrul time of CPU Architecture and OS further more, It suggests the solution aiming the communication in the other CPU or OS

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4C
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• pp.326-332
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• 2002

To transfer the large size of data more quickly among cluster nodes, the lightweight messaging scheme has been developed. VIA(Virtual Interface Architecture) allows that user can directly communicate with network devices without any interference of kernel and has become a communication protocol for clusters. But one must spend a lot of time to be skillful with it because of difficulties of programming. Therefore, we propose an easier library called EVIL(Easy-to-use Virtual Interface Library) that developers can easily deal with. We evaluated the performance of EVIL, Native VIA, TCP/IP respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.697-699
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• 2001

최근에 클러스터 시스템 사용이 보편화되어 가고 있지만 클러스터를 구성하고 있는 노드 사이의 통신이 여전히 전체 성능 향상의 병목요인으로 지적되고 있다. 현재 클러스터 시스템의 노드간 통신은 TCP 프로토콜을 이용하고 있는데, 동질적이고 전송에러를 무시할 수 있는 클러스터 통신망에는 적합하지 않다. TCP의 단점을 극복하기 위하여 클러스터를 위한 다양한 사용자 수준 인터페이스가 제안되고 구현되었다. 이 중 Inter, Compaq, Microsoft가 주축이 되어 정의한 VIA는 SAN 환경에 적합하도록 기존의 소프트웨어 오버헤드를 줄인 사용자 수준의 통신 프로토콜이다. 본 논문에서는 현재 리눅스에서 사용가능한 사용자 영역 RPC 구조를 살펴보고, SOVIA(Socket/VIA)를 하부 전송 프로토콜로 사용하여 RPC의 성능을 개선하는 방법을 제안한다. 개선한 RPC는 VIA의 성능을 사용하면서 RPC 프로그래밍에는 변화가 없으므로 VIA를 지원하는 분산 프로그래밍 환경으로 적합하다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.11a
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• pp.27-27
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• 2007

Cu via fill 도금 시, void, seam과 같은 내부 defects는 공정 중 신뢰성을 떨어뜨리며, 전기신호 전달속도를 느리게 한다. 또한 Cu via fell 도금 공정 중 발생하는 과도한 Cu 표면 도금층은 wafer thenning 공정의 생산성 저하와 공정 비용 상승을 유발한다. 3D Interconnection용 직경 30${\mu}$m, 깊이 120${\mu}$m (Aspect Ratio : 4) Via를 이용하여 정류방법, 전류 parameter, 첨가제 조성에 따른 Cu via felling 특성과 overburden두께 변화를 실험적으로 검증하였다.

• Proceedings of the Korea Water Resources Association Conference
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• 2005.09a
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• pp.555-556
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• 2005

• Proceedings of the Ginseng society Conference
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• 1980.09a
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• pp.9-16
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• 1980

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.71-76
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• 2015

Recently, light emitting diodes (LEDs) have been studied to improve their efficiencies for the uses in various fields. Particularly in the aspect of chip structure, via hole type vertical LED chip is developed for improvement of light output power, and heat dissipations. However, current vertical type LEDs have still drawback, which is current concentration around the n-contact holes. In this research, to solve this phenomenon, we introduced isolation layer under n-contact electrodes. With this sub-electrode, even though the active area was decreased by about 2.7% compared with conventional via-hole type vertical LED, we could decrease the forward voltage by 0.2 V and wall-plug efficiency was improved approximately 4.2%. This is owing to uniform current flow through the area of n-contact.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.76-81
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• 2011

A new via cutting structure in 2-layer DRAM package substrate has been fabricated to lower its power distribution network(PDN) impedance. In new structure, part of the via is cut off vertically and its remaining part is designed to connect directly with the bonding pad on the package substrate. These via structure and substrate design not only provide high routing density but also improve the PDN impedance by shortening effectively the path from bonding pad to VSSQ plane. An additional process is not necessary to fabricate the via cutting structure because its structure is completed at the same time during a process of window area formation. Also, burr occurrence is minimized by filling the via-hole inside with a solder resist. 3-dimensional electromagnetic field simulation and S-parameter measurement are carried out in order to validate the effects of via cutting structure and VDDQ/VSSQ placement on the PDN impedance. New DRAM package substrate has a superior PDN impedance with a wide frequency range. This result shows that via cutting structure and power/ground placement are effective in reducing the PDN impedance.