• Agribusiness and Information Management
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• v.9 no.2
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• pp.1-11
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• 2017

Introduction: To analyze the impact of marketing losses on efficiency in transacting banana in Kurnool district of SRZ in Andhra Pradesh and to assess the opinions of the farmers on the constraints in transacting banana. Research back ground, Materials and Methods: The study relies exclusively on primary information obtained from the banana farmers of Kurnool District. Purposive sampling procedure was followed for the selection of the study area. Top two mandals in the district and top two villages in each mandal are selected in accordance with the area under cultivation of banana. Probability proportion to size was followed regarding the selection of sample farmers and accordingly 60 marginal, 37 small and 23 other farmers were selected and thereby, the total sample size was 120. Result and Discussion: Three marketing channels were identified in the marketing of banana in Kurnool district viz., Producer ${\rightarrow}$ Local-exporter ${\rightarrow}$ Wholesaler ${\rightarrow}$ Retailer ${\rightarrow}$ Consumer (Channel-I), Producer ${\rightarrow}$ Wholesaler ${\rightarrow}$ Cart-vendor ${\rightarrow}$ Consumer (Channel-II) and Producer ${\rightarrow}$ Juice-holder ${\rightarrow}$ Consumer (Channel-III). With the inclusion of marketing losses in the price spread analysis of banana in all the three channels, the marketing costs of all the intermediaries were increased and thereby, the farmer's share in consumer's rupee and Net Marketing Margins of the agencies are on the decline. So, without inclusion of marketing losses, the farmer's share in consumer's rupee and Net Marketing Margins of all the agencies are overvalued. The higher the marketing losses, the more is the negative impact on farmer's net selling price, net marketing margins of the intermediaries and marketing efficiency. The sample farmers are facing major problems in marketing of banana like frequent price fluctuations, unorganized marketing and lack of transportation facilities on priority basis. Suggestions: It is suggested to educate the farmers regarding the optimum maturity index for harvest, use of mechanical harvesters, proper placement of fruits during storage and ripening, better packaging and cushioning technologies to absorb shocks during transportation, strengthening of storage facilities and transport facilities, encourage co-operative marketing etc., to promote marketing efficiency of banana in the study area.

• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.451-460
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• 2005

We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low-level simulation to understand the tradeoffs between energy, latency, and area. The domain specific modeling technique defines a high-level model by identifying various components and parameters specific to a domain that affect the system-wide energy dissipation. A domain is a family of architectures and corresponding algorithms for a given application kernel. The high-level model also consists of functions for estimating energy, latency, and area that facilitate tradeoff analysis. Design space exploration(DSE) analyzes the design space defined by the domain and selects a set of designs. Low-level simulations are used for accurate performance estimation for the designs selected by the DSE and also for final design selection We illustrate our methodology using a family of architectures and algorithms for matrix multiplication. The designs identified by our methodology demonstrate tradeoffs among energy, latency, and area. We compare our designs with a vendor specified matrix multiplication kernel to demonstrate the effectiveness of our methodology. To illustrate the effectiveness of our methodology, we used average power density(E/AT), energy/(area x latency), as themetric for comparison. For various problem sizes, designs obtained using our methodology are on average $25\%$ superior with respect to the E/AT performance metric, compared with the state-of-the-art designs by Xilinx. We also discuss the implementation of our methodology using the MILAN framework.