• ETRI Journal
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• v.37 no.4
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• pp.772-779
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• 2015

This paper presents a power-efficient hardware realization for a motion estimation technique that is based on the full-search block matching algorithm (FSBMA). The considered input is the quarter common intermediate format of digital video. The mean of absolute difference (MAD) is the distortion criteria employed for the block matching process. The conventional architecture considered for the hardware realization of FSBMA is that of the shift register-based 2-D systolic array. For this architecture, a conservative approximation technique is adapted to eliminate unnecessary MAD computations involved in the block matching process. Upon introducing the technique to the conventional architecture, the power and complexity of its implantation is reduced, while the accuracy of the motion vector extracted from the block matching process is preserved. The proposed architecture is verified for its functional specifications. A performance evaluation of the proposed architecture is carried out using parameters such as power, area, operating frequency, and efficiency.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.411-418
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• 2009

Vector quantization algorithm based on fuzzy clustering has been widely used in the field of data compression since the use of fuzzy clustering analysis in the early stages of a vector quantization process can make this process less sensitive to its initialization. However, the process of fuzzy clustering is computationally very intensive because of its complex framework for the quantitative formulation of the uncertainty involved in the training vector space. To overcome the computational burden of the process, this paper introduces an array architecture for the implementation of fuzzy vector quantization (FVQ). The arrayarchitecture, which consists of 4,096 processing elements (PEs), provides a computationally efficient solution by employing an effective vector assignment strategy during the clustering process. Experimental results indicatethat the proposed parallel implementation providessignificantly greater performance and efficiency than appropriately scaled alternative array systems. In addition, the proposed parallel implementation provides 1000x greater performance and 100x higher energy efficiency than other implementations using today's ARMand TI DSP processors in the same 130nm technology. These results demonstrate that the proposed parallel implementation shows the potential for improved performance and energy efficiency.

• The Journal of Korea Robotics Society
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• v.1 no.2
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• pp.197-202
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• 2006

We present the synergy effect of humanoid robot walking down on a slope and support vector machines in this paper. The biped robot architecture is highly suitable for the working in the human environment due to its advantages in obstacle avoidance and ability to be employed as human substitutes. But the complex dynamics in the robot and ground makes robot control difficult. The trajectory of the zero moment point (ZMP) in a biped walking robot is an important criterion used for the balance of the walking robots. The ZMP trajectory as dynamic stability of motion will be handled by support vector machines (SVM). Three kinds of kernels are also employed, and each result from these kernels is compared to one another.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.153-162
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• 1995

When vector quantization is used in low rate image coding (e.g., R<0.5), the primary problem is the tremendous computational complexity which is required to search the whole codebook to find the closest codevector to an input vector. Since the number of code vectors in a vector quantizer is given by an exponential function of the dimension. i.e., L=2$^{nR}$ where Rn. To alleviate this problem, a multiple shell structure of hypercube feature maps (MSSHFM) is proposed. A binary HFM of k-dimension is composed of nodes at hypercube vertices and a multiple shell architecture is constructed by surrounding the k-dimensional hfm with a (k+1)-dimensional HFM. Such a multiple shell construction of nodes inherently has a complete tree structure in it and an efficient partial search scheme can be applied with drastically reduced computational complexity, computer simulations of still image coding were conducted and the validity of the proposed method has been verified.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.7B
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• pp.771-779
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• 2011

It is expected that many heterogeneous wireless systems, such as 3GPP LTE systems, WiMAX systems and WLAN systems, will coexist in the next generation wireless communication environments. Integrated radio resource management and seamless vertical handoff (VHO) should be supported to provide integrated communication services over multi-radio access networks. A new class of adaptive VHO system that views the handoff problem as a pattern recognition problem is proposed. In this paper, we propose a unified radio resource management (URRM) architecture and Support Vector Machine (SVM) based vertical handoff decision system. Extensive simulation studies show the proposed VHO algorithm outperforms RSS based VHO algorithms in terms of throughput and service cost.

• International Journal of Computer Science & Network Security
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• v.21 no.6
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• pp.1-6
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• 2021

Recently, pre-trained convolutional neural network CNNs have been widely used and applied for medical image classification. These models can utilised in three different ways, for feature extraction, to use the architecture of the pre-trained model and to train some layers while freezing others. In this study, the ResNet18 pre-trained CNNs model is used for feature extraction, followed by the support vector machine for multiple classes to classify medical images from multi-classes, which is used as the main classifier. Our proposed classification method was implemented on Kvasir and PH2 medical image datasets. The overall accuracy was 93.38% and 91.67% for Kvasir and PH2 datasets, respectively. The classification results and performance of our proposed method outperformed some of the related similar methods in this area of study.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.601-604
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• 1999

We propose a new hierarchical motion estimator architecture that supports the advanced prediction mode of recent low bit-rate video coders such as H.263 and MPEG-4. In the proposed VLSI architecture, a basic searching unit (BSU) is commonly utilized for all hierarchical levels to make a systematic and small sized motion estimator. Since the memory bank of the proposed architecture provides scheduled data flow for calculating 8$\times$8 block-based sum of absolute difference (SAD), both a macroblock-based motion vector (MV) and four block-based MVs are simultaneously obtained for each macroblock in the advanced prediction mode. The proposed motion estimator gives similar coding performance compared with full search block matching algorithm (FSBMA) while achieving small size and satisfying the advanced prediction mode.

• Journal of Korean Association for Spatial Structures
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• v.3 no.3 s.9
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• pp.111-120
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• 2003

Tension members is a type of effective structural member, which is often used in large span structures. The structure systems composed with tension members are combined in various way and specific formations. So, there are need to research into the formations of tension structure and the type of adaptation in tension structure architectures. The structure systems with tension members were considered as tension main system, vector system and tension supported bending system, comprehensively. And tension structures were classified into the formation of tension structure with uniaxial or multiaxial line tension member, with surface member, with hybrid member of line and surface, concerning the flow of tension force. In each the formation of tension structure, the typical adaptations to architecture were also investigated through architecture examples. The type of the formation can be used to plan an architecture with respect to the flow of tension force and structural feature.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.414-418
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• 2016

In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1541-1550
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• 2004

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.