• Electronics and Telecommunications Trends
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• v.32 no.6
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• pp.57-65
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• 2017

Neural network based AI computing is a promising technology that reflects the recognition and decision operation of human beings. Early AI computing processors were composed of GPUs and CPUs; however, the dramatic increment of a floating point operation requires an energy efficient AI processor with a highly parallelized architecture. In this paper, we analyze the trends in processor architectures for AI computing. Some architectures are still composed using GPUs. However, they reduce the size of each processing unit by allowing a half precision operation, and raise the processing unit density. Other architectures concentrate on matrix multiplication, and require the construction of dedicated hardware for a fast vector operation. Finally, we propose our own inAB processor architecture and introduce domestic cutting-edge processor design capabilities.

• Journal of the Society of Naval Architects of Korea
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• v.44 no.4
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• pp.370-378
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• 2007

In this study. a numerical analysis has been performed for the turbulent flow around a 15,000TEU twin-skeg container ship using a commercial CFD code. FLUENT. The computed results have been compared with the model test data from MOERI. We investigated viscous resistance coefficient. wake distribution and characteristics of the shear flow according to the grid numbers. Although the free surface is approximated by the plane of symmetry in this work. the calculated axial velocity and transverse vector show a good agreement with the MOERI experimental data except for the region of 0.9 level of axial velocity at the propeller plane. The numerical analysis show that commercial CFD code is useful tool for the evaluation of complex hull form with twin-skegs.

• Journal of Power Electronics
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• v.14 no.3
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• pp.608-620
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• 2014

In this paper, an adaptive neural phase-locked loop (AN-PLL) based on adaptive linear neuron is proposed for grid-connected doubly fed induction generator (DFIG) synchronization. The proposed AN-PLL architecture comprises three stages, namely, the frequency of polluted and distorted grid voltages is tracked online; the grid voltages are filtered, and the voltage vector amplitude is detected; the phase angle is estimated. First, the AN-PLL architecture is implemented and applied to a real three-phase power supply. Thereafter, the performances and robustness of the new AN-PLL under voltage sag and two-phase faults are compared with those of conventional PLL. Finally, an application of the suggested AN-PLL in the grid-connected DFIG-decoupled control strategy is conducted. Experimental results prove the good performances of the new AN-PLL in grid-connected DFIG synchronization.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.415-418
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• 2004

This paper describes a VLSI implementation of BLAST detection for MIMO-OFDM systems. To achieve high speed requirement, we propose the fully pipeline architecture for BLAST structure. This design is implemented using $0.18{\mu}m$ CMOS technology. For a 4-transmit and 4-receive antennas system, it takes $7.5{\mu}s$ to calculate nulling vector and detection order from 48 channel matrixes.

• Journal of Korean Institute of Industrial Engineers
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• v.28 no.3
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• pp.319-330
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• 2002

We consider BMAP/G/1 queueing system with N-policy and multiple vacations. We derive the vector generating functions of the queue length in a factorized form and interpret the factorization. We also derive the mean queue length.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

• The KIPS Transactions:PartD
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• v.10D no.3
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• pp.359-366
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• 2003

Although the reuse of the cached data for scrolling the map reduces the amount of passed data between client and server, it needs the conversions of data coordinates, selective deletion of objects, cache compaction and object structuring step in the clients. The conversion is a time- intensive operation due to limited resources of mobile phones such as low computing power, small memory. Therefore, in order to control the map efficiently in the vector map service based mobile phones, it is necessary to study the methods which reuse cached objects for reducing wireless network bandwidth and overwhelming the limited resources of mobile phones as well. This paper proposes the methods of reusing pre-received spatial objects for map control in the mobile vector map service system based on client-server architecture. The experiments conducted on the Web GIS systems with real data show that the proposed method is appropriate to map services for mobile phone. We also analyze the advantages and drawbacks between the reuse of cached data and transmission of raw data respectively.

• Journal of the Korea Society of Computer and Information
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• v.16 no.2
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• pp.9-16
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• 2011

GPU computing is emerging in high performance application area since it can easily exploit massive parallelism in a way of cost-effective computing. The power method which finds the eigen vector of a given matrix is widely used in various applications such as PageRank for calculating importance of web pages. In this research we made the power method efficiently parallelized on GPU and also suggested how it can be improved to enhance its performance. The power method mainly consists of matrix-vector product and it can be easily parallelized. However, it should decide the convergence of the eigen vector and need scaling of the vector subsequently. Such operations incur several calls to GPU kernels and data movement between host and GPU memories. We improved the performance of the power method by means of reduced calls to GPU kernels, optimized thread allocation and enhanced decision operation for the convergence.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.39-44
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• 2008

Scan architecture is very effective design-for-testability technique that is widely used for high testability, however, it requires so much test time due to test vector shifting time. In this paper, an efficient scan test method is presented that is based on the Illinois scan architecture. The proposed method maximizes the common input effect via a scan chain selection scheme. Experimental results show the proposed method requires very short test time and small data volume by increasing the efficiency of common input effect.

• International Journal of Naval Architecture and Ocean Engineering
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• v.7 no.4
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• pp.699-707
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• 2015

The ice-resistance estimation technique for icebreaking ships had been studied intensively over recent years to meet the needs of designing Arctic vessels. Before testing in the ice model basin, the estimation of a ship's ice resistance with high reliability is very important to decide the delivered power necessary for level ice operation. The main idea of previous studies came from several empirical formulas, such as Poznyak and Ionov (1981), Enkvist (1972) and Shimansky (1938) methods, in which ice resistance components such as icebreaking, buoyancy and clearing resistances were represented by the integral equations along the Design Load Water Line (DLWL). The current study proposes a few modified methods not only considering the DLWL shape, but also the hull shape under the DLWL. In the proposed methodology, the DLWL shape for icebreaking resistance and the hull shape under the DLWL for buoyancy and clearing resistances can be directly considered in the calculation. Especially, when calculating clearing resistance, the flow pattern of ice particles under the DLWL of ship is assumed to be in accordance with the ice flow observed during ice model testing. This paper also deals with application examples for a few ship designs and its ice model testing programs at the AARC ice model basin. From the comparison of results of the model test and the estimation, the reliability of this estimation technique has been discussed.