• Journal of the Semiconductor & Display Technology
• /
• v.3 no.2
• /
• pp.5-9
• /
• 2004

Microcircuit fabrication requires precise control of impurities in tiny regions of the silicon. These regions must be interconnected to create components and VLSI circuits. The patterns to define such regions are created by lithographic processes. In order to image features smaller than 70 nm, it is necessary to employ non-optical technology (or next generation lithography: NGL). One such NGL is extreme ultra-violet lithography (EUVL). EUVL transmits the pattern on the wafer surface after reflecting ultra-violet through mask pattern. If particles exist on the blank mask, it can't transmit the accurate pattern on the wafer and decrease the reflectivity. It is important to care the blank mask. We removed the particles on the wafer using focused ion beam (FIB). During removal, FIB beam caused damage the multi layer mask and it decreased the reflectivity. The relationship between particle removal and reflectivity is examined: i) transmission electron microscope (TEM) observation after particle removal, ii) reflectivity simulation. It is found that the image mode of FIB is more effective for particle removal than spot and bar mode.

• ETRI Journal
• /
• v.24 no.2
• /
• pp.161-171
• /
• 2002

This paper proposes a novel decision feedback differential phase detection (DF-DPD) for M-ary DPSK. A conventional differential phase detection method for M-ary Differential Phase Shift Keying (DPSK) can simplify the receiver architecture. However, it possesses a poorer bit error rate (BER) performance than coherent detection because of the prior noisy phase sample. Multiple-symbol differential detection methods, such as maximum likelihood differential phase detection, Viterbi-DPD, and DF-DPD using L-1 previous detected symbols, have attempted to improve BER performance. As the detection length, L, increases, the BER performance of the DF-DPD improves but the complexity of the architecture increases dramatically. This paper proposes a simplified DF-DPD architecture replacing the conventional delay and additional architecture with an accumulator. The proposed architecture also improves BER performance by minimizing the current differential phase noise through the accumulation of previous differential phase noise samples. The simulation results show that the BER performance of the proposed architecture approaches that of a coherent detection with differential decoding.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.05a
• /
• pp.613-616
• /
• 1999

An active-matrix LCD using thin film transistors (TFTs)has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the new set of capacitance models on the pixel operations can be effectively analyzed, The set of models which is adopted from VLSI interconnections calculate more precise capacitance. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• Proceedings of the KIEE Conference
• /
• 1998.07g
• /
• pp.2206-2208
• /
• 1998

The modular Lateral Information Propagation Networks(LIPN) has been designed. The LIPN has shown to be useful for interpolation of information[3]. The problem is the fact that only the small number of nodes can be implemented in a IC chip with the circuit VLSI technology. The proposed modular architecture is for enlarging the neural network through inter module connections. For such inter module connections, the host(computer or logic) mediates the exchange of information among modules. Also border nodes in each module have capacitors for temporarily retaining the information from outer modules. The LIPN with $4{\times}4$ modules has been designed and simulation of interpolation with the designed LIPN has been done.

• ETRI Journal
• /
• v.36 no.4
• /
• pp.643-653
• /
• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• ETRI Journal
• /
• v.36 no.4
• /
• pp.635-642
• /
• 2014

Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 1999.11a
• /
• pp.278-281
• /
• 1999

In this paper, Squential circuit was implemented by decision diagram that can analyze and test large amount of functions easily. First of all, Memery device of multiple valued squential circuit was used D F/F, implemented with CMOS current mode. The opreation property of this circuit involved by PSPICE simulation. The result of Decision Diagram sequential circuit is simple and regular for selecting wire routing and posesses the property of analyze, testing. so it suitable for VLSI implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 1999.11a
• /
• pp.534-537
• /
• 1999

This paper describes a design of pipelined adaptive decision-feedback equalizer (PADFE) for high bit-rate wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of ADFE by using delayed least-mean-square (DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of ADFE including filter laps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters (filter tap, coefficient and internal bit-width, etc.) and equalization performance (bit error rate, convergence speed, etc.) are analyzed by algorithm-level simulation using COSSAP. The PADFE was designed using VHDL and Synopsys, and mapped into two ALTERA FLEX10k100 FPGAs.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.3
• /
• pp.766-772
• /
• 1999

With the increase of portable system and high-density IC, power consumption of VLSI circuits is very important factor in design process. Power estimation is required in order to estimate the power consumption. A simple and correct solution of power estimation is to use circuit simulation. But it is very time consuming and inefficient way. Probabilistic method has been proposed to overcome this problem. Transition density using probability was an efficient method to estimate power consumption using BDD and Boolean difference. But it is difficult to build the BDD and compute complex Boolean difference. In this paper, we proposed Propowest. Propowest is building a digraph of circuit, and easy and fast in computing transition density by using modified COP algorithm. Propowest provides an efficient way for power estimation.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3199-3201
• /
• 1999

Convolutional coding with Viterbi decoding is known as a powerful method for forward error correction among many kinds of channel coding methods. This paper presents a soft decision Viterbi decoder which has systolic array trace-back architecture[1]. Soft decision is known as more effective method than hard decision and most of digital communication systems use soft decision. The advantage of using a systolic array decoder is that the trace-back operation can be accomplished continuously in an array of registers in a pipe-line fashion, instead of waiting for the entire trace-back procedure to be completed at each iteration. Therefore it may be suitable for faster communication system. We described operations of each module of the decoder and showed results of the logic synthesis and functional simulation.