• Journal of the Korean institute of surface engineering
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• v.29 no.6
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• pp.809-815
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• 1996

$Y_2O_3$-based metal-insulator-semiconductor (MIS) structure on p-Si(100) has been studied. Films were prepared by UHV reactive ionized cluster beam deposition (r-ICBD) system. The base pressure of the system was about $1 \times 10^{-9}$ -9/ Torr and the process pressure $2 \times 10^{-5}$ Torr in oxygen ambience. Glancing X-ray diffraction(GXRD) and in-situ reflection high energy electron diffracton(RHEED) analyses were performed to investigate the crystallinity of the films. The results show phase change from amorphous state to crystalline one with increasingqr acceleration voltage and substrate temperature. It is also found that the phase transformation from $Y_2O_3$(111)//Si(100) to $Y_2O_3$(110)//Si(100) in growing directions takes place between $500^{\circ}C$ and $700^{\circ}C$. Especially as acceleration voltage is increased, preferentially oriented crystallinity was increased. Finally under the condition of above substrate temperature $700^{\circ}C$ and acceleration voltage 5kV, the $Y_2O_3$films are found to be grown epitaxially in direction of $Y_2O_3$(1l0)//Si(100) by observation of transmission electron microscope(TEM). Capacitance-voltage and current-voltage measurements were conducted to characterize Al/$Y_2O_3$/Si MIS structure with varying acceleration voltage and substrate temperature. Deposited $Y_2O_3$ films of thickness of nearly 300$\AA$ show that the breakdown field increases to 7~8MV /cm at the same conditon of epitaxial growing. These results also coincide with XPS spectra which indicate better stoichiometric characteristic in the condition of better crystalline one. After oxidation the breakdown field increases to 13MV /cm because the MIS structure contains interface silicon oxide of about 30$\AA$. In this case the dielectric constant of only $Y_2O_3$ layer is found to be $\in$15.6. These results have demonstrated the potential of using yttrium oxide for future VLSI/ULSI gate insulator applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.90-98
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• 2013

The stereo system based on local matching is very popular due to its algorithmic simplicity, however it is limited to apply to various applications because it shows poor quality with low matching rates. In this paper, we propose and design a realtime stereo system based on an adaptive support-weight and the system shows low error rates and realtime performance. Generally, in the adaptive support-weight algorithm the intermediate computing results can not be reused to reduce the number of computations. In this research we modify the scheduling to reuse the intermediate results for the better performance by processing rows and columns separately. The nonlinear functions such as exponential or arc tangent have been designed with piecewise linear and step functions by empirical simulations and error analysis. The proposed architecture is composed of 9 processing elements for realtime performance. The proposed stereo system has been designed and synthesized using Donbu Hitek 0.18um standard cell library and can run up to 350Mhz operation frequency (33 frames per second) with 424K gates.

• The Journal of the Korea Contents Association
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• v.9 no.11
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• pp.90-99
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• 2009

This paper presents the implementation of RFID EPC global network educational system based on using 900MHz air interface between the reader and the active tag. The software of reader and the active tag is developed on embedded environment, and the software of PC controlling the reader is based on window OS operated as the server. The ATmega128 VLSI chip is used for the processor of the reader and the active tag. As the development environment, AVR compiler is used for the reader and the active tag of which the programming language is C. The visual C++language of the visual studio on the PC activated as the server is used for development language. Main functions of this system are to control tag containing EPC global Data by PC through the reader, to obtain information of tag through the internet and to read/write data on tag memory. Finally the data written from the active tag's memory is sent to the PC via the reader as "read" operation and compare the received data with one already sent to the tag. Software implementation of 900MHz EPC global RFID educational system is done on the basis of these functions.

• The Journal of Engineering Research
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• v.6 no.1
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• pp.111-124
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• 2004

The advanced semiconductor technology and electronic design automation(EDA) tools make it possible to implement the system on the programmable logic devices. The electronic design method is also changing from schematic capture to hardware description language. In this paper, I present the architecture of multi-dimensional digital filter which can be efficiently implemented on PLDs. This is based on the former research results which are called algorithm decomposition technique. Algorithm decomposition technique is used to obtain the computational primitive from the state space equations of the multi-dimensional digital filtering algorithm. The obtained computational primitive is designed with VHDL. This can be used to implement the filtering system as a component. The designed filtering system is implemented on the PLD. Therefore, the filter can be upgradable on system. It is greatly reduced the time-to-market time of the system that is based on the multi-dimensional filter.

• Journal of the Korea Society of Computer and Information
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• v.14 no.10
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• pp.23-29
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• 2009

This paper presents the development of embedded network educational system. This is an educational equipment which enables user to have training over Network Configuration and Embedded network programming practice on Internet environment. The network education system is developed on embedded environment. based on using ethernet interface. On the development environment. PAX255 VLSI chip is used for the processor, the ADSv1.2 for debugging, uC/OS276 for RTOS. The system software was developed using C language. The ping program provided an educational environment for the student to compile and load it to run after doing practice of demonstration behavior. Afterwards programming procedure starts the step-by-step training just like the demonstration function. In other words, programming method how to design the procedure of ARP operation and ICMP operation is explained.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.687-692
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• 2009

This paper presents the development of RFID educational system based on 900MHz air interface between the reader and the active tag. The software of reader and the active tag is developed on embedded environment, and the software of PC controlling the reader is based on window OS operated as the server. The ATmega128 VLSI chip is used for the processor of the reader and the active tag. As the development environment, AVR compiler is used for the reader and the active tag of which the programming language is C. The visual C++language of the visual studio on the PC activated as the server is used for development language. Main functions of this system are to control tag containing EPC global Data by PC through the reader, to obtain information of tag through the internet and to read/write data on tag memory. Software design of 900MHz RFID/USN educational system is done on the basis of these functions.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.11
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• pp.979-983
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• 2013

The three-dimensional measurement method of confocal systems is a spot scanning method which has a high resolution and good illumination efficiency. However, conventional confocal systems had a weak point in that it has to perform XY axis scanning to achieve FOV (Field of View) vision through spot scanning. There are some methods to improve this problem involving the use of a galvano mirror [1], pin-hole array, etc. Therefore, in this paper we propose a method to improve a parallel mode confocal system using a micro-lens and pin-hole array in a dual microscope configuration. We made an area scan possible by using a combination MLA (Micro Lens Array) and pin-hole array, and used an objective lens to improve the light transmittance and signal-to-noise ratio. Additionally, we made it possible to change the objective lens so that it is possible to select a lens considering the reflection characteristic of the measuring object and proper magnification. We did an experiment using 5X, 2.3X objective lens, and did a calibration of height using a VLSI calibration target.

• Journal of Internet Computing and Services
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• v.3 no.3
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• pp.87-93
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• 2002

A complex network and a parallel computer are made up of interconnected switching units. The role of a switching unit is to set up a connection between an input port and an output port, according to the routing information. We proposed our switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. We have analysed the maximum throughput of the revised switch. Our analyses have shown that under the uniform random traffic load, the FIFO discipline is limited to 70%, The switching system consists of an input control unit, a switch unit and an output control unit. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt the new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased by about 11% when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL using Max＋plusII. We also designed our test environment including micro computers, the base station, and the proposed architecture. We proposed a new architecture of the Banyan switch for BISDN networks and parallel computers.

• Journal of Internet Computing and Services
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• v.8 no.4
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• pp.51-59
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• 2007

This paper presents the development of RFID educational system based on using 900MHz air interface between the reader and the active tag. The software of reader and the active tag is developed on embedded environment, and the software of PC controlling the reader is based on window OS operated as the server. The AT89C51ED2 VLSI chip is used for the processor of the reader and the active tag. As the development environment, Keil compiler is used for the reader and the active tag of which the programing language is C. The visual C language of the visual studio on the PC activated as the server is used for development language. To verify the function of the system, PC gets the tag's identification number through the reader and send the data to with the active tag memory a certain contents as "wite" operation. Finally the data written from the active tag's memory is sent to the PC via the reader as "read" operation and compare the received data with one already sent to the tag.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.165-175
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• 2010

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.