• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -1
• /
• pp.313-316
• /
• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
• /
• pp.7-10
• /
• 2004

This paper describes techniques to implement low-cost adapt ive Pipelined LMS filter for ASIC implement ions of high communication receivers. Power consumpiton can be reduced using a careful selection of architectural, algorithmic, and VLSI circuit techlifue A Pipelined architecture for the strength-reduced algorithm is then developed via the relaxed look-ahead transformation. This technique, which is an approximation of the conventional look-ahead compution, maintains the functionality of the algorithm rather than the input-output behavior Convergence maiysis of the Proposed architecture has been presented and support via simulation results. The resulting pipelined adaptive filter achives a higher though put requires lower power as compared to the filter using the serial algorithm.

• 전기전자학회논문지
• /
• 제16권3호
• /
• pp.197-202
• /
• 2012

As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 센서 박막재료 반도체재료 기술교육
• /
• pp.119-123
• /
• 2002

A new modular Lateral Information Propagation Networks(LIPN) has been designed. The LIPN has shown to be useful for reconstruction of information[3]. The problem is the fact that only the small number of nodes can be implemented in a IC chip with the circuit VLSI technology. The proposed modular architecture is propagated the neural network through inter module connections. For such inter module connections, the host (computer or logic) mediates the exchange of information among modules. Also border nodes in each module have capacitors for temporarily retaining the information from outer modules. The LIPN with $4{\times}4$ modules has been designed and simulation of interpolation with the designed LIPN has been done.

• The Journal of Korean Physical Therapy
• /
• 제13권2호
• /
• pp.257-264
• /
• 2001

To take the Far-infrared(FIR) ray which is a optimized wavewlength and strength, at first, it is to be induced the characteristic algorithm and the computerized programing of FlR radiating materials. In this study, we induced that the formular of optimized FIR with physical, mathematical logic and theory, especially, Plank, Kirchhoff, Wien, Stefan-Boltzmann's logic and law. In the long run the formular was induced with mathematical integration. since we had to know the molecular wavelength. Base on the induced formular as above, we programmed the optimized FlR radiating computerized program, it would be useful to design semiconductor( VLSI) as the FlR instrument center control system.

• 한국항행학회논문지
• /
• 제7권2호
• /
• pp.206-210
• /
• 2003

본 논문에서는 최신의 미세공정인 0.18um CMOS 공정을 이용한 표준 셀 라이브러리를 설계하고, 이를 P&R(Placement and Routing) CAD 툴에 사용할 수 있도록 포팅한다. 제작결과를 검증하기 위하여 간단한 테스트칩을 제작하였으며 설계에 사용된 표준 셀 라이브러리는 0.18um 아남반도체의 공정이다. 이러한 설계 및 제작과정을 통하여 최신의 미세공정을 이용하여 디지털 시스템의 자동설계가 가능함을 확인하였다.

• 한국통신학회:학술대회논문집
• /
• 한국통신학회 2006년도 하계종합학술발표회 논문 초록집
• /
• pp.417-417
• /
• 2006

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
• /
• pp.791-793
• /
• 1999

제어 컴퓨터의 고장으로 인해 인명이나 재산에 치명적 영향을 미치는 safety-critical 실시간 시스템을 제어하고 모니터링하기 위해 디지털 컴퓨터의 사용은 점점 일반화되고 있다. 특히, VLSI 기술의 급격한 발달로 인해 하드웨어가 초소형화 되고 대량생산이 가능해진 현실에서 이러한 제어 컴퓨터의 극대화된 신뢰도 요구를 만족시키기 위해 막중한 하드웨어 여분(hardware redundancy)이 널리 사용되고 있는 실정이다. 본 논문에서는 N개의 다중 모듈(multi-module)로 이루어진 하드웨어 여분의 운영 모드를 분석하고 각 운영 모드에서 고장이 발생할 경우 모드의 전환과 그로 인한 신뢰도의 변화를 계산할 것이다. 그리고 간단한 시뮬레이션을 통해 전환된 여러 모드 중 가장 우수한 신뢰도를 갖는 모드를 평가하게 된다.

• Journal of information and communication convergence engineering
• /
• 제8권5호
• /
• pp.570-574
• /
• 2010

A thinning algorithm changes a binary fingerprint image to one pixel width. A thinning stage occupies 40% cycle of 32-bit RISC microprocessor system for a fingerprint identification algorithm. Hardware block processing is more effective than software one in speed, because a thinning algorithm is iteration of simple instructions. This paper describes an effective hardware scheme for thinning stage processing using the Verilog-HDL in $160\times192$ Pixel Array. The ZS algorithm was applied for a thinning stage. The hardware scheme was designed and simulated in RTL. The logic was also synthesized by XST in FPGA environment. Experimental results show the performance of the proposed scheme.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권1호
• /
• pp.118-125
• /
• 2016

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.