• Journal of the Korea Society for Simulation
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• v.11 no.2
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• pp.55-66
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• 2002

VHDL has been. widely used in modeling and simulation of hardware designs. However, complex relationship between components of the designs makes the VHDL modeling problem very difficult. Furthermore, after the initial creation of VHDL models, they evolve into many versions over their lifetime. To cope with such difficulties, this paper proposes a new methodology for the management of VHDL models supporting versions. Its conceptual bases are system entity structure and relational database. Within the methodology, a family of hierarchical structures of a design is organized in the form of VHDL model structure. It is, in turn, represented in the form of relational tables. Once the model structure is built in such a way, a specific simulation model which meets design objective is pruned from the model structure. The details of VHDL codes are systematically synthesized by combining it with the primitive models in a model base. These algorithms are also defined in terms of relational algebraic operations.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.19-33
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• 2002

In this Paper, we described the Parwan CPU using a VHDL at the behavioral level and then described by connecting CPU components at the dataflow level. Finally, we simulated to verify of execution of a CPU processor using a test-bench method. A presented design method was to enable information exchange of design and representation of operation were very exact and simple. Also. a documentation of design was available and it was easy that verify a operation of designed processor. The behavioral description of VHDL aids designer as we verify our understanding of the designed system, while the dataflow description can be used to verify the bussing and register structure of the design.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1013-1016
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• 1998

A method for generation of design verification tests from behavior-level VHDL program is presented. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements. So for large, complex system, it is difficult problem to test or simulation. In this paper, we proposed a new hardware design verification method. For this method generates control flow graph(CFG.) and process modeling graph(PMG) in the given under the testing VHDL program. And this method proved very effective that all the assumed design errors could be detected.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.180-187
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• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.197-199
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• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1346-1353
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• 1996

In this paper, we propose a modeling method for the flip-flops and test generation algorithms to detect the faults in the sequential circuits using VHDL in the high-level design environment. RS, JK, D and T flip-flops are modeled using data flow types. The sequence of micro-operation which is the basic structure of a chip-level leads to a control point where varnishing occurs to one of two micro- operation sequence. In order to model the fault of one micro-operation(FMOP) that perturb another micro-operation effectively, the concept of goal trees and some heuristic rules are used. Given a faulty FMOP or fault of control point (FCON), a test pattern is generated by fault sensitization, path sensitization and determination of the imput combinations that will justify the path sensitization. The fault models are restricted to the data flow model in the ARCHITECTURE statement of VHDL. The proposed algorithm is implemented in the C language and its efficiency is confirmed by some examples.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.509-512
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• 2005

The aim of this work is to design a real-time reusable image enhancement architecture for video signals, based on a spatial processing of the video sequence. The VHDL hardware description language has been used in order to make possible a top-down design methodology. By adding proposed algorithms to the LPR(License Plate Recognition) system, the system is implemented with reliability and safety on a rainy day. Spartan-2E XC2s300E is used as implementation platforms for real-time system.

• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.2
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• pp.232-238
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• 2013

The vehicle system is a multi-domain system that requires many branches of science and engineering. Therefore the development of the vehicle system requires the use of design methodologies that utilize simulations, which have grown increasingly sophisticated in recent years. Our research group proposed a simulation modeling method based on the VHDL-AMS language. This paper describes how VHDL-AMS is used to model of vehicle fuel consumption simulation. The fuel consumption is shown using proposed simulation model on the Japanese 10-15 mode. We examine the influence of the vehicle system with electrical load and hill climb resistance in the vehicle running resistance.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1073-1076
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• 1998

This paper describes implementation of a highlevel graphic design entry tool operating on X Window system The proposed design entry tool includes visual schematic entry, hierarchical modeling ability and VHDL source code generation. Experimental results show the efficiency of the proposed design system

• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.45-52
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• 1999

In this thesis, a packer is proposed and designed for removing the bottle-neck effect and easy signal processing using a new algorithm with the operation frequency of 54MHz. To verify the performance of the proposed packer, DCT coefficient encoding block with ROM table using a combinational logic is designed and its output data are used the input data of the packer. Circuits in this thesis are designed by using VHDL code and its modeling and simulation are performed by SYNOPSYS tool using $0.65{\mu}m$ rule.