• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.127-134
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• 2006

This paper describes a fully hardware realization of vector controller for the permanent magnet synchronous motor (PMSM) using high density field programmable gate mays (FPGA). In the proposed system, the vector controller including vector transformation , PI regulator, position and speed measurement, current measurement, and space vector PWM blocks is implemented in a FPGA using a VHSIC hardware description language (VHDL). The experimental results using a 1.1kW PMSM are provided to show the validity of the proposed system.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.3
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• pp.43-48
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• 2000

In this paper, CPLD(Complex Programmable Logic Device) controller designed with VHDL is developed. With the controller, the harmonics from 3 phase diode rectifier are suppressed and power factor is also improved. The input current of diode rectifier is drawn from the ac mains only during the period in the ac cycle when the instantaneous voltage is greater than the voltage across the dc-link capacitor. The three bidirectional switches rated at very small power are installed in a conventional three phase diode rectifier. Using CPLD controller, an idle current charges to capacitors continuously. Results of simulation and experimental demonstrate a reduction of harmonics, a improvement of power factor and THD.

• Journal of Advanced Navigation Technology
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• v.13 no.1
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• pp.97-103
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• 2009

In this paper, the structure and detailed specifications of the HDR-WPAN physical layer have been analyzed and the block module of transmitter and receiver have been also designed, and analyzed the performance as well. In the process of transmitter design, it concentrated on all possibility of modulation of QPSK, DQPSK and 16/32/64QAM-TCM, which could be available for mode selection due to the transmission rate. In addition to the receiver module, DQPSK and TCM decoding algorithm is mainly concerned. After designing the transceiver MODEM using VHDL, we have programmed on the platform board and verified the functions of the MODEM. Some experimental results showed that it can be considered a possibility of data communication without error over SNR 22dB.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.183-189
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• 2019

Despite its low cost, ARM is widely used in smartphones, digital cameras, home network devices, and wireless technologies because of its low power consumption and reliable performance. The domestic memory semiconductor design technology is in the world's highest level, but that of the processor is far less than that, which results in the technology unbalance between the memory and the processor. When designing a processor, exception and interrupt capabilities are requisite, but this is often omitted in the research stage. However, exception processing and interrupts must be included in order for the processor to function fully. In this paper, we design a 32-bit ARMv4 family of processors with exception handling and interrupts using VHDL and verify with ModelSim. As a result, ARM's exception and interrupts are successfully performed.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.187-193
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• 2020

Floating point arithmetic in microprocessor is the computation of addition, subtraction, multiplication, and division of floating point data to improve accuracy. In general, when designing a processor, floating point instructions are often excluded because of its complexity and only integer instructions are provided. However, in order to carry out the computations for not only engineering and technical operations but also artificial intelligence and neural networks that are in the spotlight today, floating point operations must be included. In this paper, we design a 32-bit ARMv4 family of processors with floating-point arithmetic instructions using VHDL and verify with ModelSim. As a result, ARM's floating point instructions are successfully executed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4A
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• pp.325-329
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• 2007

In this paper, the modem based on EIA-709.2-A PL of powerline communication techniques which are considered to be important technologies for in-home control network systems was implemented via VHDL. In order to have the robust properties against existing noises over powerline channels, the information data using eight symbols was transmitted by transmitter and the receiver is composed of matched filter, averager, decision and detection parts in order to detect the right data from the received signals. The implemented PLC transceiver was downloaded into Altera's EP1S25C672 FPGA and the operation was verified successfully.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.71-76
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• 2001

In this paper we propose the Digital Automatic Gain Controller for IEEE 802.11a-High-speed Physical Layer in the 5 GHz Band. The input gain it estimated by calculating the energy of the training symbol that it a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.8
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• pp.764-770
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• 2001

In this paper, we propose a novel PCI bus based parallel fuzzy inference system for transferring and inferencing the large volumes of fuzzy data in high speed. For this, the PCI 9050 interface chip is used to connect a local bus design as a PCI target core using FPGA to the PCI bus. We design and implement the PCI target core by using VHDL to be processed in parallel by considering the points of parallelyzing each element of the membership functions and each block of the condition and/or consequent parts. The proposed system can be used in a system requiring a rapid inference time in a real-time system or pattern recognition on the large volume of satellite images that have many inference variables in the condition and consequent parts.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.345-347
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• 2003

본 논문에서는 디지털 보호 계전기에 쓰이는 필터 중에서 최소 자승 알고리즘을 이용한 고성능 FIR 필터를 설계하였다. 기존의 DFT필터와 MATLAB 시뮬레이션을 이용하여 비교하였으며 FIR 필터의 VHDL모델 및 합성에 중점을 두었다. FIR 필터는 기본적으로 유한개의 임펄스 응답이 이루어지기 때문에 기타 다른 필터에 비하여 안정도가 높으며 선형적인 위상을 가지기 때문에 차단 주파수 대역의 왜곡현상을 없앨 수 있는 장점을 가지고 있다. 여러 가지 알고리즘으로 구현한 FIR 필터를 시뮬레이션 한 결과 최소 자승 알고리즘이 가장 우수한 결과를 나타내었다. 기본적으로 디지털 보호 계전기에서 디지털 필터의 기능은 사고 전압, 전류로부터 60Hz의 기본파 추출 CT, PT 왜곡 및 DC offset을 제거하는데 있다. 본 논문에서는 이러한 기능을 가지면서 샘플링 주파수와 차수를 같게 하여 FIR 필터와 DFT 필터의 주파수 응답과 연 산 속도를 비교 하였다. 본 논문에서 설계된 최소 자승 알고리즘을 이용한 FIR 필터는 같은 조건의 DFT필터에 비해 1고조파와 2고조파의 차이가 10db 이상 더 우수 하였으며 연산 속도 또한 2배 이상 좋은 결과를 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.277-284
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• 2001

Viterbi algorithm is widely used in digital communication system for FEC(forward error correction). Each communication systems based on the Viterbi algorithm use specific Viterbi decoder which has different code parameter values. Even if Viterbi decoder has the same code parameters, it can be varied by the design architecture adopted. We propose the parameterized VHDL model generator for the efficiency of the design. It makes it possible to achieve shorter design time and lower design cost. The model generator searches the design space available and finds out the optimal design point to generate a decoder model.