• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.48-57
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• 2020

MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single poly EEPROM cells have a large cell size. In this paper, a 110nm MTP cell using a vertical PIP capacitor is proposed. The erase operation of the proposed MTP cell uses FN tunneling between FG and EG, and the program operation uses CHEI injection method, which reduces the MTP cell size to 1.09㎛2 by sharing the PW of the MTP cell array. Meanwhile, MTP memory IP required for applications such as USB type-C needs to operate over a wide voltage range of 2.5V to 5.5V. However, the pumping current of the VPP charge pump is the lowest when the VCC voltage is the minimum 2.5V, while the ripple voltage is large when the VCC voltage is 5.5V. Therefore, in this paper, the VPP ripple voltage is reduced to within 0.19V through SPICE simulation because the pumping current is suppressed to 474.6㎂ even when VCC is increased by controlling the number of charge pumps turned on by using the VCC detector circuit.

• Journal of IKEEE
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• v.26 no.3
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• pp.422-429
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• 2022

A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuse OTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logic devices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three masks which are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And since the 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. In addition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, which is a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied through the PMOS power switching circuit after packaging, so that the number of package pins can be reduced.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.6
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• pp.483-489
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• 2014

In this study, experiments were conducted for micro pattern printing to combine solution atomization process and stencil printing based on electrospray deposition. The stencil mask fabricated by etching the photosensitive glass placed below 0.3 mm distance to substrate has 100 um line width. The process parameters of electrospray deposition system for the atomization of the solution are applied voltage and supply flow rate of the solution. Meniscus angle of cone-jet was optimized by varying the supply flow rate from 0.3 ml/hr to 0.7 ml/hr. Voltage condition was verified having symmetric cone-jet angle and no pulsation at 8.5 kV applied voltage. In addition, a number of micro patterns are printed using a single 1 step process by solution atomization process. Variable line width of approximate 100 um was confirmed by changing conditions of solution atomization regardless of the pattern size of stencil mask.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.11
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• pp.63-69
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• 1995

A novel programming architecture for antifuse FPGA(Field Programmable Gate Array) is described. This architecture prevents programming transistors from breakdown which occurs due to high voltage across the transistors during antifuse programming. Extra mask and processes can be avoided using this proposed architecture. To reduce the applied voltage across the terminals of programming transistors, different voltage ranges are supplied to vertical and horizontal tracks; between programming voltage Vp and Vp/2 for vertical tracks and between Vp/2 and 0V for horizontal tracks. Therefore, Maximum voltage across the programming transistors is half of the programming voltage and an designated antifuse can be programmed by applying maximum voltage for vertical track and minimum voltage for horizontal track while others are subjected to voltage difference below Vp/2.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• Bulletin of the Korean Space Science Society
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• 2011.04a
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• pp.20.3-20.3
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• 2011

감마선폭발 (Gamma Ray Burst) 사건에서 아직 관측이 안되고 있는 초기 방출 광자에 대한 연구를 위하여 Ultra Fast Flash Observatory (UFFO) 인공위성 프로젝트가 제안되었다. 이 탑재체의 주요 기기로써, 감마선 폭발의 위치를 측정하기 위하여 coded mask 기반의 X-ray 광시야각 망원경인 UFFO Burst Alert X-ray Trigger Telescope (UBAT)와 감마선 폭발의 자외선 및 가시광 초기 후광관측을 위한 Slewing Mirror Telescope(SMT)가 있다. UFFO 프로젝트는 한국이 주도하고 미국, 대만, 러시아, 덴마크, 스페인, 프랑스, 노르웨이, 폴란드가 참여하는 9개국 국제공동연구이며, 2011년 11월 UFFO pathfinder가 러시아 인공위성인 Lomonosov에 실려 발사될 예정이다. 차세대 UFFO-100는 2015년 발사 목표로 연구가 시작되고 있다. UFFO pathfinder의 현재 진행상황과 가능한 연구에 대하여 논의한다.

• The Korean Journal of Applied Statistics
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• v.25 no.3
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• pp.471-483
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• 2012

One of the most important problems in cluster analysis is the selection of variables that truly define cluster structure, while eliminating noisy variables that mask such structure. Brusco and Cradit (2001) present VS-KM(variable-selection heuristic for K-means clustering) procedure for selecting true variables for K-means clustering based on adjusted Rand index. This procedure starts with the fixed number of clusters in K-means and adds variables sequentially based on an adjusted Rand index. This paper presents an updated procedure combining the VS-KM with the automated K-means procedure provided by Kim (2009). This automated variable selection procedure for K-means clustering calculates the cluster number and initial cluster center whenever new variable is added and adds a variable based on adjusted Rand index. Simulation result indicates that the proposed procedure is very effective at selecting true variables and at eliminating noisy variables. Implemented program using R can be obtained on the website "http://faculty.knou.ac.kr/sskim/nvarkm.r and vnvarkm.r".

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.465-468
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• 1998

For porous silicon layer to be used as active layer in various devices, it is necessary to be formed locally along with a designed pattern on the wafer. However, there is still no suitable masking layer to withstand against the high concentration of HF for a time of some minutes up to some hours during the anodic process effectively. In this work, we investigated the property of selectivity between p$^{+}$ and n layers to form localized porous silicon even without a mask by the difference of the anodic I-V characteristics on the doping level and doping type. The width of the pattern made in the sample was 2mm, and the formed porous silicon layer was observed by SEM to see the morphology on the cross section below the surface. As the results, it was found that the selectivity was reasonable for the pattern size over 100.mu.m.m.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.112-116
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• 2006

In this presentation we will describe two core elements, which combination gives a new approach to layout verification; they are a computational algorithm for modeling of photolithographical processes and a method for physical layout verification that uses output contours of that algorithm. Utilization of this approach allows to improve the quality of LCOS/AM OLED backplanes physical verification, because it considers discrepancies between mask features and printed contours on a wafer.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1162-1165
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• 2006

In this paper, the characteristics of polycrystalline silicon thin-film transistors (poly- Si TFTs) fabricated on polymer substrates are investigated. The a-Si films was laser annealed by using a XeCl excimer laser and a four-mask-processed poly-Si TFT was fabricated with fully self-aligned top gate structure. The fabricated nMOS TFT showed field-effect mobility of ${\sim}30\;cm^2/Vs$, on/off ratio of $10^5$ and threshold voltage of 5 V.