• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.80-86
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• 2014

A low-noise readout circuit is studied for 2-D capacitive microbolometer focal plane arrays (FPAs). In spite of the merits of the integration method, a simple and effective pixelwise readout circuit without integration is used for input circuit because of a small pixel size and narrow noise bandwidth. To reduce the power consumption and the kT/C noise, which is the dominant noise of the capacitive microbolometer FPAs with small capacitance, a new correlated double sampling (CDS) is used for columnwise circuit. The proposed circuit has been designed using a $0.35-{\mu}m$ 2-poly 4-metal CMOS process for a microbolometer array with a pixel size of $50{\mu}m{\times}50{\mu}m$. The proposed circuit effectively reduces the kT/C noise and the other low-frequency noise of microbolometer, and the noise characteristics of the fabricated chip have been verified by measurements. The rms noise voltage of the proposed circuit is reduced from 30 % to 55 % compared to that of the simple readout input circuit, and the noise equivalent temperature difference (NETD) of the proposed circuit is very low value of 21.5 mK.