• Electronics and Telecommunications Trends
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• v.35 no.5
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• pp.43-56
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• 2020

The 5G system standardization body has been developing standard functions to provide ultra-high speed, ultra-high reliability, ultra-low latency, and ultra-connected services. In 3GPP Rel-16, which was recently completed, this system has begun to develop ultra-high reliability and ultra-low latency communication functions to support the vertical industry. It is expected that the trend in the adoption of mobile communication by the vertical industry will continue with the introduction of 5G. In this paper, we present the industrial Internet-of-Things (IIoT) service scenarios and requirements for the adoption of 5G systems by the vertical industry and the related standardization trend at present. In particular, we introduce the 5G time-sensitive networking standard technology, a core technology for realizing 5G-based smart factories, for IIoT services.

• Electronics and Telecommunications Trends
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• v.36 no.6
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• pp.13-24
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• 2021

Industrial networks has been developing various technologies from fieldbus technology to industrial Ethernet and time-sensitive networking. The industry expects that the 5G mobile network will solve the diverse and highly specific industrial site requirements. Accordingly, 3GPP has been developing standard functions to provide ultra-high reliability, ultra-high speed, ultra-connection, and ultra-low latency services, and 3GPP Rel-16 began developing ultra-low latency and ultra-high reliability communication functions for 5G mobile networks to support vertical industries. In this paper, we show the related standardization trends and requirements to apply industrial IoT service scenarios to 5G mobile networks, and in particular, we introduce 5G system features and extended 5G system architecture to provide time sensitive communication and time synchronization services.

• Progress in Superconductivity and Cryogenics
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• v.20 no.4
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• pp.6-10
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• 2018

Low-noise amplifiers in the radio-frequency (RF) band based on the direct current (DC) superconducting quantum interference device (SQUID) can be used for quantum-limited measurements in precision physics experiments. For the prediction of peak-gain frequency of these amplifiers, we need a reliable design formula for the resonance frequency of the microstrip circuit. We improved the formula for the resonance frequency, determined by parameters of the DC SQUID and the input coil, and compared the design values with experimental values. The proposed formula showed much accurate results than the conventional formula. Minor deviation of the experimental results from the theory can be corrected by using the measured geometrical parameters of the input coil line.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.349-352
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• 2001

In this paper, novel device structure in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA) for ultra pn junction formation. Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20 nm for arsenic dosage (2$\times$10$^{14}$ $\textrm{cm}^2$), excimer laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm.

• Journal of the Korean Society for Heat Treatment
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• v.17 no.2
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• pp.78-86
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• 2004

Effects of the annealing parameters on the formation of ferrites transformed at low temperatures were studied in cold-rolled ultra low carbon steels with niobium and/or chromium. Niobium and chromium were found to be effective in the formation of the low temperature transformation ferrites. The low temperature transformation ferrites more easily formed when both higher annealing temperature and longer annealing time, allowing substitutional alloying elements to distribute between phases, are in combination with faster cooling rate. It was found from EBSD study that the additions of niobium or chromium resulted in the increase in the numbers of high angle grain boundaries and the decrease in those of the low angle grain boundaries in the microstructures. Both granular bainitic ferrite and bainitic ferrite were characterized by the not clearly etched grain boundaries in light microscopy because of the low angle grain boundaries.

• Electronics and Telecommunications Trends
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• v.34 no.6
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• pp.108-122
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• 2019

Ultra-low latency networking is a technology that reduces the end-to-end latency related to transport time-sensitive or mission-critical traffic in a network. As the proliferation of the fourth industrial revolution and 5G mobile communications continues, ultra-low latency networking is emerging as an essential technology for supporting various network applications (such as industrial control, tele-surgery, and unmanned vehicles). In this report, we introduce the ultra-low-latency networking technologies that are in progress, categorized by application area, and examine their up-to-date standard status.

• Journal of the Semiconductor & Display Technology
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• v.13 no.3
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• pp.13-19
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• 2014

Phosphoric acid was used as etching agent instead of conventional peroxide - based chemicals for forming pattern of ultra definition display. Etchant was synthesized by mixing etching agent, oxidation agent, buffer solution, and additive into solvent, deionized water. Thicknesses of copper, main metal of ultra definition display, for etching, were 10,000 and $30,000{{\AA}}$. Etch stop of good low skew for proper pattern formation has been occurred at the content ratio of phosphoric acid 60 - 64%, nitric acid 4 - 5%, additive(potassium acetate) 1 - 3%. Buffer solution(acetic acid) decreased the metal contact angle $63.07^{\circ}$ to $42.49^{\circ}$ for benefiting pattern formation. Content variations on four components (phosphoric acid, nitric acid, acetic acid, potassium acetic acid) of the etchant with storage time were within 3 wt% after 24 hrs of etching work.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.157-158
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• 2002

A surface hardenable low alloy carbon steel was implanted with medium energy (20 - 50KeV) $N_2^+$ ions to produced a modified hardened surface. The implantation conditions were varied and are given in several doses. The surface hardness of treated and untreated steels were measured using depth sensing ultra micro indentation system (UMIS). It is shown that the hardness of nitrogen ion implanted steels varied from 20 to 50GPa depending on the implantation conditions and the doses of implantation. The structure of the modified surfaces was examined by X-ray photoelectron spectroscopy (XPS). It was found that the high hardness on the implanted surfaces was as a result of formation of non-equilibrium nitrides. High-resolution XPS studies indicated that the nitride formers were essentially C and Si from the alloy steel. The result suggests that the ion implantation provided the conditions for a preferential formation of C and Si nitrides. The combination of evidences from nano-indentation and XPS, provided a strong evidence for the existence of $sp^3$ type of bonding in a suspected $(C,Si)_xN_y$ stoichiometry. The formation of ultra hard surface from relatively cheap low alloy steel has significant implication for wear resistance implanted low alloy steels.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.208-211
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• 2005

This paper presents an ultra-low partial discharge(PD) measurement system that has been accepted as a non-destructive method to estimate electrical insulation of low-voltage electric devices. The PD measurement system is composed of a coupling network, a low noise amplifier, and associated electronics. A shielding box is used to make a better condition against electromagnetic interference. A low cut-off frequency of the coupling network was 1MHz(-3 dB). Calibration tests on laboratory set-up have shown that the PD measurement system has a stable sensitivity of 11.4mV/pC. In an application experiment on a low-voltage induction motor(5HP), we could detect 0.77pC level of partial discharge pulse at the applied voltage of AC 664 V$_{peak}$.