• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.239-244
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• 2013

This paper presents a design of the CMOS LDO regulator with a UVLO protection function for a high speed PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. UVLO block between the power transistor and the power supply is added for a low input protection function. Also, UVLO block showed normal operation with turn-off voltage of 2.7V and turn-on voltage of 4 V in condition of 5 V power supply. Proposed circuit generated fixed 3.3 V from a supply of 5V. From SPICE simulation results using a $1{\mu}m$ high voltage CMOS technology, simulation results were 5.88 mV/V line regulation and 27.5 uV/mA load regulation with load current 0 mA to 200 mA.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.4
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• pp.195-200
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• 2006

The conventional discrete circuit for ABS/TCS system was examined and the problems of the system were analyzed by computer simulation. In order to improve the performance of ABS/TCS system, interface IC which has error compensation, comparator and under voltage lock-out circuit was designed and their electrical characteristics were investigated. The voltage regulator was included to compensate the temperature variation in the temperature range from $-20^{\circ}C$ to $120^{\circ}C$ for automobile environment. ABS and brake signal were separated using the duty factor of same frequency or different frequencies. UVLO(Under Voltage Lock-Out) circuit and constant current circuit were applied for the elimination of noise, and protection circuit was applied to cut the excess current off. Layout for IC fabrication was designed to enhance the electrical performance of ABS/TCS system. Layout was consisted of 11 masks, arrayed effectively 8 pads to reduce the current loss. We can see that the result of layout simulation was better than the result of bread board.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.627-633
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• 2015

We designed of a LDO regulator with a OVP and UVLO protection function for a PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. The proposed LDO regulator is designed for low voltage input power protection. Proposed LDO circuit generated fixed 2.5 V from a supply of 3.3V. It was designed with 3.3 V power supply using a $0.35{\mu}m$ CMOS technology. SPICE simulation results showed that the proposed circuit provides 0.713 mV/V line regulation with output 2.5 V ~ 3.9 V and $8.35{\mu}V/mA$ load regulation with load current 0 mA to 40 mA.

• Journal of the Korean Society of Industry Convergence
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• v.21 no.6
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• pp.265-271
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• 2018

DC-DC buck converter is a critical building block in the power management integrated circuit (PMIC) architecture for the portable devices such as cellular phone, personal digital assistance (PDA) because of its power efficiency over a wide range of conversion ratio. To ensure a safe operation, avoid unexpected damages and enhance the reliability of the converter, fully-integrated protection circuits such as over voltage protection (OVP), under voltage lock out (UVLO), startup, and thermal shutdown (TSD) blocks are designed. In this paper, these three fully-integrated protection circuit blocks are proposed for use in the DC-DC buck converter. The buck converter with proposed protection blocks is operated with a switching frequency of 1 MHz in continuous conduction mode (CCM). In order to verify the proposed scheme, the buck converter has been designed using a 180 nm CMOS technology. The UVLO circuit is designed to track the input voltage and turns on/off the buck converter when the input voltage is higher/lower than 2.6 V, respectively. The OVP circuit blocks the buck converter's operation when the input voltage is over 3.3 V, thereby preventing the destruction of the devices inside the controller IC. The TSD circuit shuts down the converter's operation when the temperature is over $85^{\circ}C$. In order to verify the proposed scheme, these protection circuits were firstly verified through the simulation in SPICE. The proposed protection circuits were then fabricated and the measured results showed a good matching with the simulation results.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.125-127
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• 2008

기존의 LED(Light Emitting Diode)를 이용한 LCD(Liquid Crystal Display) 백라이트 유닛은 LED에 과전류가 흐르면 소자의 파손이 발생하고 무부하시 불필요한 전력소모가 발생하는 경우가 있어 보호회로가 필요하였다. 그래서 본 논문은 보호회로를 이용한 LCD 백라이트 유닛용의 LED 구동회로를 제안한다. 제안된 보호회로는 2가지로 첫 번째 보호회로는 무부하시 소비전력을 줄이는 보호회로 이다. 시뮬레이션 결과 무부하시 피드백 제어부 IC(Integrated Circuit)의 전원전압 $V_{cc}$를 UVLO(Under Voltage Lock Out)전압 이하로 강하시켰다. 그래서 무부하시 소비되는 전력을 줄일 수 있었다. 두번째 보호회로는 과전류시 보호회로 이다. 시뮬레이션 결과 과전류시 SCR이 온 되어 피드백 제어부 IC의 전원전압 $V_{cc}$를 UVLO전압 이하로 강하시켰다. 따라서 과전류시 LED 동회로 소자의 파손을 방지할 수 있는 장점이 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.7-14
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• 2008

In this paper, we designed the HVIC(High Voltage Gate Driver IC) which has improved noise immunity characteristics and high driving capability. Operating frequency and input voltage range of the designed HVIC is up to 500kHz and 650V, respectively. Noise protection and schmitt trigger circuit is included in the high-side level shifter of designed IC which has very high dv/dt noise immunity characteristic(up to 50V/ns). And also, rower dissipation of high-side level shifter with designed short-pulse generation circuit decreased more that 40% compare with conventional circuit. In addition, designed HVIC includes protection and UVLO circuit to prevent cross-conduction of power switch and sense power supply voltage of driving section, respectively. Protection and UVLO circuit can improve the stability of the designed HVIC. Spectre and Pspice circuit simulator were used to verify the operating characteristics of the designed HVIC.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.219-225
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• 2014

This paper describes an IC for Power Factor Correction. It can use electrical appliances which convert power from AC to DC. The power factor can be influenced not only phase difference of voltage and current but also sudden change of current waveform. This circuit enables current wave supplied to load by close to sinusoidal and minimum phase difference of voltage and current waveform. A self oscillated 10[kHz]~100[kHz] pulse signal converted to PWM waveform and it chops rectified full wave AC power which flows to load device. The multiplier and zero current detector circuit, UVLO, OVP, BGR circuits were designed. This IC has been designed and whole chip simulation use 0.5[um] double poly, double metal 20[V] CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.58-65
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• 2009

In this paper, we designed high voltage gate drive IC including dead time circuit in which capacitors controlled rising time and falling time, and schimitt-triggers controlled switching voltage. Designed High voltage gate drive IC improves an efficiency of half-bridge converter by decreasing dead time variation against temperature and has variable dead time by the capacitor value. and its power dissipation, which is generated on high side part level shifter, has decreased 52 percent by short pulse generation circuit, and UVLO circuit is designed to prevent false-operation. We simulated by using Spectre of Cadence to verify the proposed circuit and fabricated in a 1.0um process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.60-67
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• 2010

We designed Average Current Control PFC IC which has make the average value of boost inductor current became the shape of sine wave. Designed IC has fixed frequency of 75kHz to meet EMI standard requirement. And also RC compensation loop has been designed into the error amp and the current amp, in order that it has wide bandwidth for high speed control. And we use the oscillator which generates by square wave and triangle wave, and add to UVLO, OVP, OCP, TSD which is in order to operate stability. We simulated by using Spectre of Cadence to verify the unity power factor function and various protection circuits and fabricated in a $1{\mu}m$ High Voltage(20V) CMOS process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.122-122
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• 2009

최근 PC의 성능이 향상되면서, 고성능의 전원공급 장치가 요구되고 있다. 특히 CPU에 대전력을 공급하는 싱크로너스 벅 컨버터는 파워 MOSFET을 구동하기 위해 별도의 구동 IC가 필요하다. 본 논문은 adaptive 지연을 이용하여 파워 MOSFET을 구동하는 싱크로너스 벅 구동 IC를 설계하였다. 고정밀도의 밴드캡 기준회로와 비교기를 이용하여 30 ns의 adaptive 지연을 생성하며, 전력소모를 줄이기 위해 저전압에서 동작하는 UVLO(under voltage lock out)를 설계하였다. 또한 상단 파워 MOSFET을 구동하기 위하여 부트스트랩 방식을 이용하며, 부트스트랩 다이오드를 IC 내부에 내장하여 컨버터의 설계비용을 줄였다. 설계한 구동 IC의 동작 전압 범위는 8 V - 15 V이며, 출력 전류는 최대 2A이다. 싱크로너스 벅 구동 IC는 $0.5\;{\mu}m$ BiCMOS(Bipolar-CMOS) 공정 파라미터를 사용하여 설계되었으며, 시뮬레이션은 Cadence사의 Spectre를 이용하였다.