• Journal of Electrochemical Science and Technology
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• v.14 no.4
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• pp.388-396
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• 2023

Photoelectrochemical (PEC) water splitting is a vital source of clean and sustainable hydrogen energy. Moreover, the large-scale H₂ production is currently necessary, while long-term stability and high PEC activity still remain important issues. In this study, a GaN-based photoelectrode was modified by an additional NH₃ treatment (900℃ for 10 min) and its PEC behavior was monitored. The bare GaN exhibited a highly crystalline wurtzite structure with the (002) plane and the optical bandgap was approximately 3.2 eV. In comparison, the NH₃-treated GaN film exhibited slightly reduced crystallinity and a small improvement in light absorption, resulting from the lattice stress or cracks induced by the excessive N supply. The minor surface nanotexturing created more surface area, providing electroactive reacting sites. From the surface XPS analysis, the formation of an N-Ga-O phase on the surface region of the GaN film was confirmed, which suppressed the charge recombination process and the positive shift of E_FB. Therefore, these effects boosted the PEC activity of the NH₃-treated GaN film, with J values of approximately 0.35 and 0.78 mA·cm^-2 at 0.0 and 1.23 V_RHE, respectively, and an onset potential (V_on) of -0.24 V_RHE. In addition, there was an approximate 50% improvement in the J value within the highly applied potential region with a positive shift of V_on. This result could be explained by the increased nanotexturing on the surface structure, the newly formed defect/trap states correlated to the positive V_on shift, and the formation of a GaO_xN_1-x phase, which partially blocked the charge recombination reaction.

• Applied Microscopy
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• v.47 no.3
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• pp.105-109
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• 2017

The effect of temperature and vanadium metal concentration on the electronic and thermoelectric properties of Si in the diamond cubic structure has been investigated using a combination of density functional theory simulations and the semi classical Boltzmann's theory. The BotzTrap code within the constant relaxation time approximation has been used to obtain the Seebeck coefficient and other transport properties of interest for alloys of the structure $Si_{1-x}V_x$, where x is 0, 0.125, 0.25, 0.375, and 0.5. The thermoelectric properties have been extracted for a temperature range of 300 K to 1,000 K. The general trend with V atom substitution for Si causes the Seeback coefficient to increase and the thermal conductivity to decrease for the various alloys. The optimum values are for $Si_5V_3$ and $Si_4V_4$ alloys for charge carrier concentrations of $10^{21}cm^{-3}$ in the mid temperature range of 500~800 K. This is a very desirable effect for a promising thermoelectric and the figure of merit ZT approaches 0.2 at 600 K for the p-type $Si_5V_3$ alloy.

• International Journal of Automotive Technology
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• v.8 no.4
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• pp.395-402
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• 2007

Homogeneous Charge Compression Ignition (HCCI) shows great potential for low $NO_x$ emission but is hampered by the problem of no direct method to control the combustion process. Therefore, HCCI combustion becomes unstable easily, especially at lower and higher engine load. This paper presents a method to achieve diesel-fueled HCCI combustion, which involves directly injecting diesel fuel into the cylinder before the piston arrives at top dead center in the exhaust stroke and adjusting the valve overlap duration to trap more high temperature residual gas in the cylinder. The combustion stability of diesel-fueled HCCI combustion and the effects of engine load, speed, and valve overlap on it are the main points of investigation. The results show that: diesel-fueled HCCI combustion has two-stage heat release rate (low temperature and high temperature heat release) and very low $NO_x$ emission, combustion stability of the HCCI engine is worse at lower load because of misfire and at higher load because of knock, the increase in engine speed aids combustion stability at lower load because the heat loss is reduced, and increasing negative valve overlap can increase in-cylinder temperature which aids combustion stability at lower load but harms it at higher load.

• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.737-739
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• 1998

Gate insulators using various fluoride films were investigated for thin film transistor applications. Conventional oxide containing materials exhibited high interface states, high $D_{it}$ gives an increased threshold voltage and poor stability of TFT. To improve TFT performances, we must reduce interface trap charge density between Si and gate insulator. In this paper, we investigated gate insulators such as such as $CaF_2$, $SrF_2$, $MgF_2$ and $BaF_2$. These materials exhibited an improvement in lattice mismatch, difference in thermal expansion coefficient, and electrical stability MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 0.737%, breakdown electric field higher than 1.7MV/cm and leakage current density of $10^{-6}A/cm^2$. This paper probes a possibility of new gate insulator material for TFT application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.101-102
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• 2009

We described the growth of undoped ZnO thin films and their optical properties changing with a various growth temperature. The un doped ZnO thin films were grown on c-$Al_2O_3$ substrates using pulsed laser deposition (PLD) at room temperature, 200, 400, and $600^{\circ}C$, respectively. Field emission microscopy (FE-SEM) measurements showed that the grain size of undoped ZnO thin films are increasing as a increase of growth temperature. In addition, we were investigated that the structural and optical properties of undoped ZnO thin films by x-ray diffraction (XRD) and photoluminescence (PL) studied. Also, we could confirmed that the exciton luminescence was strongly related to charge trap by grain boundary of the samples using micro-PL measurement.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.211.1-211.1
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• 2014

Recently, the scaling of conventional planar NAND flash devices is facing its limits by decreasing numbers of electron stored in the floating gate and increasing difficulties in patterning. Three-dimensional vertical NAND devices have been proposed to overcome these issues. Atomic layer deposition (ALD) is the most promising method to deposit charge trap layer of vertical NAND devices, SiN, with excellent quality due to not only its self-limiting growth characteristics but also low process temperature. ALD of silicon nitride were studied using NH3 and silicon chloride precursors, such as SiCl4[1], SiH2Cl2[2], Si2Cl6[3], and Si3Cl8. However, the reaction mechanism of ALD silicon nitride process was rarely reported. In the present study, we used density functional theory (DFT) method to calculate the reaction of silicon chloride precursors with a silicon nitride surface. DFT is a quantum mechanical modeling method to investigate the electronic structure of many-body systems, in particular atoms, molecules, and the condensed phases. The bond dissociation energy of each precursor was calculated and compared with each other. The different reactivities of silicon chlorides precursors were discussed using the calculated results.

• Electrical & Electronic Materials
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• v.7 no.1
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• pp.25-31
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• 1994

Properties of oxynitride films reoxidized by $N_2{O}$ gas after thermal oxidation and $N_2{O}$ oxide films directly oxidized by using $N_2{O}$ gas on the bare silicon wafer have been studied. From the AES analysis, nitrogen pile-up at the interface of Si/oxynitride and Si/$N_2{O}$ oxide has observed. $N_2{O}$ oxide and oxynitride films have the self-limited characteristics. Therefore, it will be possible to obtain ultra-thin films. Nitrogen pile-up at the interfaces of Si/oxynitride and Si/$N_2{O}$ oxide strengthens film structure and improves dielectric reliability. Although fixed charge densities and interface trap densities of N20 oxide and oxynitride films have somewhat higher than those of thermal $SiO_2{O}$, $N_2{O}$ oxide and oxynitride films showed improved I-V characteristics and constant current stress.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.196-197
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• 2010

NAND형 charge trap flash (CTF) non-volatile memory (NVM) 소자가 30nm node 이하로 고집적화 되면서, 기존의 SONOS형 CTF NVM의 tunnel barrier로 쓰이는 SiO2는 direct tunneling과 stress induced leakage current (SILC)등의 효과로 인해 data retention의 감소 등 물리적인 한계에 이르렀다. 이에 따라 개선된 retention과 빠른 쓰기/지우기 속도를 만족시키기 위해서 tunnel barrier engineering (TBE)가 제안되었다. TBE NVM은 tunnel layer의 전위장벽을 엔지니어드함으로써 낮은 전압에서 전계의 민감도를 향상 시켜 동일한 두께의 단일 SiO2 터널베리어 보다 빠른 쓰기/지우기 속도를 확보할 수 있다. 또한 최근에 각광받는 high-k 물질을 TBE NVM에 적용시키는 연구가 활발히 진행 중이다. 본 연구에서는 Si3N4와 HfAlO (HfO2 : Al2O3 = 1:3)을 적층시켜 staggered의 새로운 구조의 tunnel barrier Capacitor를 제작하여 전기적 특성을 후속 열처리 온도와 방법에 따라 평가하였다. 실험은 n-type Si (100) wafer를 RCA 클리닝 실시한 후 Low pressure chemical vapor deposition (LPCVD)를 이용하여 Si3N4 3 nm 증착 후, Atomic layer deposition (ALD)를 이용하여 HfAlO를 3 nm 증착하였다. 게이트 전극은 e-beam evaporation을 이용하여 Al를 150 nm 증착하였다. 후속 열처리는 수소가 2% 함유된 질소 분위기에서 $300^{\circ}C$와 $450^{\circ}C$에서 Forming gas annealing (FGA) 실시하였고 질소 분위기에서 $600^{\circ}C{\sim}1000^{\circ}C$까지 Rapid thermal annealing (RTA)을 각각 실시하였다. 전기적 특성 분석은 후속 열처리 공정의 온도와 열처리 방법에 따라 Current-voltage와 Capacitance-voltage 특성을 조사하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.186-186
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• 2010

소자의 축소화에 따라 floating gate 형의 flash 메모리 소자는 얇은 게이트 절연막 등의 이유로, 이웃 셀 간의 커플링 및 게이트 누설 전류와 같은 문제점을 지니고 있다. 이러한 문제점을 극복하기 위해 charge trap flash 메모리 (CTF) 소자가 연구되고 있지만, CTF 메모리 소자는 쓰기/지우기 속도와 데이터 보존 성능간의 trade-off 관계와 같은 문제점을 지니고 있다. 최근, 이를 극복하기 위한 방안으로, 다른 유전율을 갖는 유전체들을 적층시킨 터널 절연막을 이용한 Tunnel Barrier Engineered (TBE) 기술이 주목 받고 있다. 따라서, 본 논문에서는 TBE 기술을 적용한 MIS-capacitor를 높은 유전율을 가지는 Al2O3와 HfO2를 이용하여 제작하였다. 이를 위해 먼저 Si 기판 위에 Al2O3 /HfO2 /Al2O3 (AHA)를 Atomic Layer Deposition (ALD) 방법으로 약 2/1/3 nm의 두께를 가지도록 증착 하였고, Aluminum을 150 nm 증착 하여 게이트 전극으로 이용하였다. Capacitance-Voltage와 Current-Voltage 특성을 측정, 분석함으로써, AHA 구조를 가지는 터널 절연막의 전기적인 특성을 확인 하였다. 또한, high-k 물질을 이용한 터널 절연막을 급속 열처리 공정 (Rapid Thermal Annealing-RTA) 과 H2/N2분위기에서 후속열처리 공정 (Post-RTA)을 통하여 전기적인 특성을 개선 시켰다. 적층된 터널 절연막은 열처리를 통해 터널링 전류의 민감도의 향상과 함께 누설전류가 감소됨으로서 우수한 전기적인 특성이 나타남을 확인하였으며, 적층된 터널 절연막 구조와 적절한 열처리를 이용하여 빠른 쓰기/지우기 속도와 전기적인 특성이 향상된 비휘발성 메모리 소자를 기대할 수 있다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.229-229
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• 2011

부유 게이트 Floating gate (FG) 플래시 메모리 소자의 단점을 개선하기 위해 전하 포획 층에 전하를 저장하는 전하 포획 플래시 메모리 Charge trap flash (CTF)소자에 대한 연구가 활발히 진행되고 있다. CTF소자는 FG플래시 메모리 소자에 비해 비례축소가 용이하고 긴 retention time을 가지며, 낮은 구동 전압을 사용하는 장점을 가지고 있다. CTF 소자에서 비례축소에 따라 단채널 효과와 펀치-쓰루 현상이 증가하는 문제점이 있다.본 연구에서는 CTF 단채널 효과와 펀치-쓰루 현상을 감소시키기 위한 방법으로 silicon-on-insulator (SOI) 기판을 사용하였으며 SOI기판에서 절연층의 깊이에 따른 전기적 특성을 고찰하였다. silicon-oxide-nitride-oxide-silicon(SONOS) 구조를 가진 CTF 메모리 소자를 사용하여 절연층의 깊이 변화에 따른 subthreshold swing특성, 쓰기-지우기 동작 특성을 TCAD 시뮬레이션 툴인 Sentaurus를 사용하여 조사하였다. 소스와 드레인의 junction depth는 20 nm 사용하였고, 절연층의 깊이는 5 nm~25 nm까지 변화하면서 절연층의 깊이가 20 nm이하인 fully depletion 소자에 비해, 절연층의 깊이가 25 nm인 소자는 partially depletion으로 인해서 드레인 전류 레벨이 낮아지고 subthreshold swing값이 증가하는 현상이 나타났다. 절연층의 깊이가 너무 얕을 경우, 채널 형성의 어려움으로 인해 subthreshold swing과 드레인 전류 레벨의 전기적성질이 SOI기판을 사용하지 않았을 경우보다 떨어지는 경향을 보였다. 절연층의 깊이가 17.5 nm인 경우, CTF소자의 subthreshold swing과 드레인 전류 레벨이 가장 좋은 특성을 보였다.