• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.113.1-113.1
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• 2014

Surface-enhanced Raman scattering (SERS) has long been projected as a powerful analytical technique for chemical and biological sensing applications. Pairing with portable Raman spectrometers makes the technique extremely appealing as real-time sensors for field application. However, the lack of reliable, uniform, low cost and ease-of-use SERS enhancement structures has prevented the wide adoption of this technique for general applications. We have discovered a novel hybrid structure based on the high-density and uniform arrays of gold nanofingers over a large surface area for SERS applications. The nanofingers are flexible and their tips can be brought together to trap molecules to mimic the biological system. We report here a rapid, simple, low-cost, and sensitive method of detecting trace level of food contaminants by using nanofinger chips based on portable SERS technique. We also present here the characterization of surface reaction of target molecules with our gold nanofinger substrates and the effect of nanofinger closing towards SERS performance. This new type of nano-structures can potentially revolutionize the medical and biologic research by providing a novel way to capture, localize, manipulate, and interrogate biological molecules with unprecedented capabilities.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.171-174
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• 1994

The drive towards ultra-large-scale integrated circuits a continuous intermetal dielectric films for multi layer interconection. Optimum condition of remote plasma enhanced chemical vapour deposition(RPECVD) was achieved by orthogonal array method. Chracteristics of SiO$_2$ films deposited by using remote PECVD with N$_2$O gas were investigated. Etching rate of SiO$_2$ films in P-echant was about 6[A/s] that was the same as the thermal oxide. The films a showed high breakdown voltage of 7(MV/cm) and a resistivity of Bx10$\^$13/[$\Omega$cm] at 7(MV/cm). The interface Trap density of SiO$_2$ has been shown excel lent properties of 5x10$\^$10/[/$\textrm{cm}^2$eV]. It was observed that the dielectric constant dropped to a value of 4. 29 for 150 [W] RF power.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.15-16
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• 2000

The gate bias stress effect of the hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) with a $SiN_x/BCB$ gate insulator have been studied. The gate planarization was carried out by spin-coating of BCB (benzocyclobutene) on Cr gates. The BCB exhibits charge trappings during a high gate bias, but the stability of the TFT is the same as conventional one when it is between -25 V and +25 V. The charge trap density in the BCB increases with its thickness.

• Electrical & Electronic Materials
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• v.5 no.3
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• pp.310-319
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• 1992

LPCVD 방법으로 625.deg.C와 560.deg.에서 증착한 다결정 실리콘에 As이온주입량을 lx$10^{13}$-lx$10^{16}$/$cm^{2}$로 변화시키면서 열처리 전, 후의 미세구조와 전기적 특성 변화를 조사하였다. 625.deg.C에서 증착한 시편은 columnar구조를 하고 있어 표면이 매우 거칠었으며 900.deg.C, 30분 열처리 후에는 As doping 농도에 관계없이 결정립 크기는 200-300.angs.정도였다. 560.deg.C에서 증착한 시편은 비정질 상태로열처리 후에는 1000.angs.이상의 큰 결정립을 갖는 타원형의 결정립으로 성장하였으며 표면이 매우 smooth하였다. 같은 doping 농도에서 전기 전도도와 Hall mobility는 비정질 상태로 증착한 시편이 큰 결정립으로 인하여 다결정 상태로 증착한 시편에 비해 크게 되었다. Grain boundary trapping model에 의해 계산한 potential barrier height는 As doping 농도가 증가함에 따라 감소하였으며 grain boundary trap density는 증착 온도, As doping 농도 및 결정립 크기에 크게 관계없이 3.6~5*$10^{12}$/$cm^{2}$로 측정되었다.

• Proceedings of the SAREK Conference
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• 2008.06a
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• pp.271-276
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• 2008

The oil trap in oil separator is one of the most important characteristics for normal operation of compressor. In this study, oil separation characteristics has been investigated for $CO_2$/PAG mixture using a gravity type of oil separator. The experimental study has been carried out in the range of oil concentration 0 to 5 weight-percent and the mixture temperature range of $0^{\circ}C$ to $15^{\circ}C$. The results obtained indicate that oil separation ratio in oil separator is increased with an increase in the oil concentration and mixture temperature.

• KEPCO Journal on Electric Power and Energy
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• v.2 no.2
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• pp.223-225
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• 2016

The newly proposed analysis method using a direct-current current-voltage (DCIV) simulation is introduced for investigating leakage current composing MOS transistor. From comparing the density and location of traps using DCIV method and investigating the leakage current of gate channel transistor, we proposed the graphical analysis method to correlate the DCIV current and leakage mechanism by the traps. And, our graphical method intuitively explains that leakage current in MOS transistor is well correlated with the DCIV current of the MOS transistor arrays due to two kinds of traps created by Fowler-Nordheim (F-N) stress and Hot carrier stress, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.106-111
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• 1996

Schottky diodes are fabricated on laser annealed and unannealed polysilicon substrate and their electrical characteristics are studied and analyzed. Current of laser annealed devices are larger than that of unannealed devices because of grain growth, decrease of grain boundary and trap density, lowering of grain boundary barrier height, decrease of dopant segregation. At low forward bias (<0.7V), currents of unanealed devices are larger. Soft breakdown voltages of laser annealed devices are larger than that of unannealed devices.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.550-552
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• 2009

The negative bias temperature instability on LTPS TFTs in a darkened and an illuminated environment was investigated. Experimental results reveal that the generation of interface state density showed no change between the different NBTI stresses. The degradation of the grain boundary trap under illumination was more significant than for the darkened environment.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.7
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• pp.760-765
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• 1992

The material properties and the TFT characteristics fabricated on SiOS12T substrate by LPCVD using SiHS14T gas were investigated. The deposition rate showed Arrhenius behavior with an activation energy of 31Kcal/mol. And the transition temperature form amorphous to crystalline deposition was observed at 570$^{\circ}C$-580$^{\circ}C$. The strong(220) texture was observed as the deposition temperature increases. XRD analysis showed that the film texture of the as-deposited polycrystalline silicon does not change after annealing at 850$^{\circ}C$. The fabricated TFT's based on the as-deposited amorphous film showed superior electrical characteristics to those of the as-deposited polycrystalline films. It is considered that the different electrical characteristics result from the difference of flat band voltage(VS1FBT) due to the interface trap density between the gate oxide and the active channel.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.5
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• pp.365-370
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• 2000

Schottky contacts on n-In$\_$0.53//Ga$\_$0.47//As have been made by metal deposition on substrates cooled to a temperature of 77K. The current-voltage and capacitance-voltage characteristics showed that the Schottky diodes formed at low temperature had a much improved barrier height compared to those formed at room temperature. The Schottky barrier height ø$\_$B/ was found to be increased from 0.2eV to 0.6eV with Ag metal. The saturation current density of the low temperature diode was about 4 orders smaller than for the room temperature diode. A current transport mechanism dominated by thermionic emission over the barrier for the low temperature diode was found from current-voltage-temperature measurement. Deep level transient spectroscopy studies exhibited a bulk electron trap at E$\_$c/-0.23eV. The low temperature process appears to reduce metal induced surface damage and may form an MIS (metal-insulator-semiconductor)-like structure at the interface.