• Journal of the Korea Society of Computer and Information
• /
• v.20 no.11
• /
• pp.31-38
• /
• 2015

Nowadays, large size flash memory drives with more than a couple of hundreds of gigabytes are common. This paper presents an efficient cache management scheme of flash translation layer, called TPC-FTL, for large size flash memory drives. Since flash drives of large size usually contain large size RAM, we can enhance the performance of page mapping cache by using more RAM for the cache. But if the size exceeds a threshold, the existing schemes are impractical for real devices, because the time for cache manipulation becomes too long. TPC-FTL manages the cache in translation page unit, not in logical page number unit used in existing schemes. Since a translation page covers a large number of logical page numbers (for example, 512 for 2KB size page), the number of cache elements can be reduced up to a practical level. A performance evaluation shows that average response time, an important performance measure, is better than existing schemes via the effect of utilizing spacial locality in addition to temporal locality.

• BMB Reports
• /
• v.49 no.4
• /
• pp.199-200
• /
• 2016

Gene regulation in the brain is essential for long-term plasticity and memory formation. Despite this established notion, the quantitative translational map in the brain during memory formation has not been reported. To systematically probe the changes in protein synthesis during memory formation, our recent study exploited ribosome profiling using the mouse hippocampal tissues at multiple time points after a learning event. Analysis of the resulting database revealed novel types of gene regulation after learning. First, the translation of a group of genes was rapidly suppressed without change in mRNA levels. At later time points, the expression of another group of genes was downregulated through reduction in mRNA levels. This reduction was predicted to be downstream of inhibition of ESR1 (Estrogen Receptor 1) signaling. Overexpressing Nrsn1, one of the genes whose translation was suppressed, or activating ESR1 by injecting an agonist interfered with memory formation, suggesting the functional importance of these findings. Moreover, the translation of genes encoding the translational machineries was found to be suppressed, among other genes in the mouse hippocampus. Together, this unbiased approach has revealed previously unidentified characteristics of gene regulation in the brain and highlighted the importance of repressive controls.

• The KIPS Transactions:PartA
• /
• v.12A no.3 s.93
• /
• pp.205-214
• /
• 2005

Flash memory is at high speed used as storage of personal information utilities, ubiquitous computing environments, mobile phones, electronic goods, etc. This is because flash memory has the characteristics of low electronic power, non-volatile storage, high performance, physical stability, portability, and so on. However, differently from hard disks, it has a weak point that overwrites on already written block of flash memory is impossible to be done. In order to make an overwrite possible, an erase operation on the written block should be performed before the overwrite, which lowers the performance of flash memory highly. In order to solve this problem the flash memory controller maintains a system software module called the flash translation layer(FTL). Of many proposed FTL schemes, the log block buffer scheme is best known so far. This scheme uses a small number of log blocks of flash memory as a write buffer, which reduces the number of erase operations by overwrites, leading to good performance. However, this scheme shows a weakness of low page usability of log blocks. In this paper, we propose an enhanced log block buffer scheme, FAST(Full Associative Sector Translation), which improves the page usability of each log block by fully associating sectors to be written by overwrites to the entire log blocks. We also show that our FAST scheme outperforms the log block buffer scheme.

• Journal of KIISE
• /
• v.42 no.4
• /
• pp.427-433
• /
• 2015

The rapid advancement of computing technology has triggered the need for fast data I/O processing and high-performance storage technology. Next generation memory technology, which we refer to as new memory, is anticipated to be used for high-performance storage as they have excellent characteristics as a storage device with non-volatility and latency close to DRAM. This research proposes NTL (New memory Translation layer) as a technology to make use of new memory as storage. With the addition of NTL, conventional I/O is served with existing mature disk-based file systems providing compatibility, while new memory I/O is serviced through the NTL to take advantage of the byte-addressability feature of new memory. In this paper, we describe the design of NTL and provide experiment measurement results that show that our design will bring performance benefits.

• Journal of the Korea Society of Computer and Information
• /
• v.24 no.2
• /
• pp.1-7
• /
• 2019

This paper presents CTP (Compact Translation Page), a compact representation of translation pages, for page mapping-based flash translation layers to improve RAM utilization and reduce the response time of solid state drives. CTP can store translation information twice in a translation page and the total number of translation pages stored in flash is reduced to half. Therefore, CTP halves the RAM size of the directory of translation pages and uses the saved RAM space for translation cache. CTP shows the best response time when compared to existing page mapping-based flash translation layers.

• International Journal of Advanced Culture Technology
• /
• v.6 no.4
• /
• pp.165-171
• /
• 2018

As the artificial intelligence (AI) plays a crucial role in machine translation (MT) which has loomed large as a new translation paradigm, concerns have also arisen if MT can produce a quality product as human translation (HT) can. In fact, several MT experimental studies report cases in which the MT product called post-editing (PE) as equally as HT or often superior ([1],[2],[6]). As motivated from those studies on translation quality between HT and PE, this study set up an experimental situation in which Korean literature was translated into English, comparatively, by 3 translators and 3 post-editors. Afterwards, a group of 3 other Koreans checked for accuracy of HT and PE; a group of 3 English native speakers scored for fluency of HT and PE. The findings are (1) HT took the translation time, at least, twice longer than PE. (2) Both HT and PE produced similar error types, and Mistranslation and Omission were the major errors for accuracy and Grammar for fluency. (3) HT turned to be inferior to PE for both accuracy and fluency.

• Proceedings of the Korean Society for Language and Information Conference
• /
• 2007.11a
• /
• pp.87-94
• /
• 2007

This paper introduces BEYTrans (Better Environment for Your TRANSlation), the first experimental environment for free online collaborative computer-aided translation. The requirements and functionalities related to individual translators and communities of translators are distinguished and described. These functionalities have been integrated in a Wiki-based complete environment, equipped with all currently possible asynchronous linguistic resources and translation aids. Functions provided by BEYTrans are also compared with existing CAT systems and ongoing experiments are discussed.

• Journal of KIISE:Computer Systems and Theory
• /
• v.36 no.6
• /
• pp.463-475
• /
• 2009

Flash memory is suitable for real time systems because of its consistent performance for random access, low power consumption and shock resistance. However, flash memory needs blocking time to perform a garbage collection to reclaim invalidated pages. Moreover, the worst-case garbage collection time is significantly longer than the best-case garbage collection time. In this paper, we propose a FTL (Flash Translation Layer) mapping scheme called KAST (K-Associative Sector Translation). In the KAST scheme, user can control the maximum association of the log block to limit the worst-case garbage collection time. Performance evaluation using simulation shows that not only KAST completes the garbage collection within the specified time but also provides about 10~15% better average performance than existing FTL schemes.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.46 no.4
• /
• pp.21-30
• /
• 2009

Fusion flash memory such as OneNAND$^{TM}$ is popular as a ubiquitous storage device for embedded systems because it has advantages of NAND and NOR flash memory that it can support large capacity, fast read/write performance and XIP(eXecute-In-Place). Besides, OneNAND$^{TM}$ provides not only advantages of hybrid structure but also multi-block erase function that improves slow erase performance by erasing the multiple blocks simultaneously. But traditional NAND Flash Translation Layer may not fully support it because the garbage collection of traditional FTL only considers a few block as victim block and erases them. In this paper, we propose an Erase Group Flash Translation Layer for improving multi-block erase function. EGFTL uses a superblock scheme for enhancing garbage collection performance and invalid block management to erase multiple blocks simultaneously. Also, it uses clustered hash table to improve the address translation performance of the superblock scheme. The experimental results show that the garbage collection performance of EGFTL is 30% higher than those of traditional FTLs, and the address translation performance of EGFTL is 5% higher than that of Superblock scheme.

• Proceedings of the Korean Society of Computer Information Conference
• /
• 2014.07a
• /
• pp.227-229
• /
• 2014

플래시 메모리는 빠른 처리 속도, 비휘발성, 저 전력, 강한 내구성 등으로 인해 최근 스마트폰, 태블릿, 노트북, 컴퓨터와 같은 여러 분야에서 많이 사용하고 있다. 최근 기존에 사용하던 NAND 플래시가 미세화 기술의 한계에 봉착함에 따라 기존 2차원 구조의 NAND플래시를 대처할 장치로 3차원 수직구조 NAND 플래시 메모리(3D Vertical NAND)가 주목받고 있다. 기존의 플래시 메모리는 데이터를 효율적으로 삽입/삭제/검색하기 위해 B-tree와 같은 색인기법을 필요로 한다. 플래시 메모리 상에서 B-tree 구현에 관한 기존 연구로서는 BFTL(B-Tree Flash Translation Layer)기법이 최초로 제안되었다. 현재 3차원 V-NAND 구조의 플래시 메모리가 시작품으로 제작되어 머지않아 양산 될 예정이다. 본 논문에서는 향후 출시될 3차원 구조의 플래시 메모리에 적합한 Octree 기반의 파일시스템을 제안한다.