• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.1
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• pp.51-58
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• 1990

NPN Si bipolar transistors with two different emitter widths are designed and fabricated. The effects of the emitter width on the small signal parameters of BJTs are measured and discussed. A new ac method for determining the current gain, the cut off frequency and the internal capacitances from the input impedance circle characteristics as a function of the varied external series resistances is presented. This method allows an accurate characterization of bipolar transistors with high current gain. The variation of the I-V curves of the emitter junction with the reverse collector junction voltages is discussed from the changes in the intsrinsic base resistances.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.637-637
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• 2013

We develop single-crystal poly(3,4-ethylenedioxythiopene nanowires using liquid-bridge-mediated nanotransfer printing via vapor phase polymerization. This direct printing method can simultaneously enable the synthesis, alignment and patterning of the nanowires from molecular ink solutions. Twoor three-dimensional complex structures of various single-crystal organic nanowires were directly fabricated over a large area using many types of molecular inks. This method is capable of generating several optoelectronic devices. LB-nTM is based on the direct transfer of various materials from a mold to a substrate via a liquid bridge between them. To demonstrate its usefulness, we used LB-nTM to fabricate nanowire field-effect transistors and arrays of 6,13-bis (triisopropyl- silylethynyl) pentacene (TIPS-PEN) nanowire field-effect transistors.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.534-536
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• 2009

We have fabricated solution-processed zinc-tin oxide thin film transistors (TFTs) and simple circuits on glass substrates. We report a solutionprocessed zinc-tin oxide TFTs on silicon wafer with mobility greater than 9 $cm^2/V{\cdot}s$ (W/L = 100/5 ${\mu}m$) and threshold voltage variation of less than 1 V after bias-stressing. Also, we fabricated solution-processed zinc-tin oxide circuits including inverters and 7-stage ring oscillators fabricated on glass substrates using the developed zinc-tin oxide TFTs.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.907-909
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• 2009

Low voltage operated top gated polymer transistors were fabricated with a high permittivity polymer, P(VDF-TrFE) and F8T2 as a gate dielectric and semiconducting layer, respectively. The operating voltage of transistors was effectively reduced under -10 V and typical threshold voltages were as low as -1 ~ -4 V with the reasonable charge carrier mobility of $10^{-3}cm^2$/Vs for the amorphous polymer. The large hysteresis in transfer curve was improved effectively by annealing at low temperature.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.896-898
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• 2009

The printed electrodes of organic thin-film transistors (OTFTs) were fabricated by screen printing using nanoparticle silver pastes. The screen printed OTFT corresponds to channel lengths between 7.6 to 82.6 ${\mu}m$ (designed L=10 to 80 ${\mu}m$) on the $150{\times}150mm^2$ paper. The channel length deviations for 40 to 80 ${\mu}m$ patterns were less than 5 %. However, the channel lengths for 10 to 30 ${\mu}m$ patterns were increased by 20 %. The screen printed bis(triisopropyl-silylethynyl) pentacene (TIPS-pentacene) OTFTs obtained had a field-effect mobility as large as 0.08 (${\pm}0.02$) $cm^2$/Vs, an on/off current ratio of $10^5$ and a subthreshold slope of 1.95 V/decade.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.918-923
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• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• Journal of Information Display
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• v.12 no.2
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• pp.109-113
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• 2011

This paper summarizes the recent fabrication and characterizations of flexible high-speed radio frequency (RF) transistors, PIN-diode single-pole single-throw switches, as well as flexible inductors and capacitors, based on single-crystalline Si nanomembranes transferred on polyethylene terephthalate substrates. Flexible thin-film transistors (TFTs) on plastic substrates have reached RF operation speed with a record cut-off/maximum oscillation frequency ($f_T/f_{max}$) values of 3.8/12 GHz. PIN diode switches exhibit excellent ON/OFF behaviors at high RF frequencies. Flexible inductors and capacitors compatible with high-speed TFT fabrication show resonance frequencies ($f_{res}$) up to 9.1 and 13.5 GHz, respectively. Robust mechanical characteristics were also demonstrated with these high-frequency passives components.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3A
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• pp.185-191
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• 2003

In this paper, we propose two CMOS composite transistors with an improved operating region by reducing the threshold voltage. The proposed composite transistorⅠand transistor Ⅱ employ a P-type folded composite transistor and a composite diode in order to decrease the threshold voltage, respectively. The limitation of the operating region of these transistors by current source is described. All circuits are simulated by Hsipice using 0.25㎛ n-well process with 2.5V supply voltage.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.3
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• pp.273-280
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• 1990

To prevent the shoot-through phenomena in a PWM inverter, a short dead time is usually provided between a pair of switching transistors in the same leg of the inverter. In this approach, the amount of the dead time is designed to meet the worst case condition of the inverter transistors and the base drive elements. So, in normal cases, relatively large portion of the dead time is unnecessary and it results in an undesirablecurrent waveform distortion and generates ripple torque on the motor shaft. In this paper, a new base drive method to remove the undesirable portion of the dead time is described. The method senses the transistor on/off states to interlock the other transistor of the leg without the external dead time. Also, for the transistors of large current rating, the Darlington drive circuit is combined to the proposed method and is tested to verify the effectiveness. The experimental results of the proposed method are described and compared with those of the conventional dead time method.