• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.19-25
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• 2008

In this study, we fabricated Organic Thin Film Transistors(OTFTs) with $C_{60}$ hole injection layer between organic semiconductor(pentacene) and metal electrode, and we compared the electrical characteristics of OTFTs with/without $C_{60}$. When the $C_{60}$ hole injection layer was introduced, the mobility and the threshold voltage were improved from 0.298 $cm^2/V{\cdot}s$ and -13.3V to 0.452 $cm^2/V{\cdot}s$ and -10.8V, and the contact resistance was also reduced. When the $C_{60}$ is inserted, the hole injection was enhanced because the $C_{60}$ prevent the unwanted chemical reaction between pentacene and Au. Furthermore, we fabricated the OTFTs using Al as their electrodes. When the OTFTs were made by only aluminum electrode, the channel were not mostly made because of the high hole injection barrier between pentacene and aluminum, but when the $C_{60}$ layer with an optimal thickness was applied between aluminum and pentacene, the device performances were obviously enhanced because of the vacuum energy level shift of Al and the consequent decrease of the hole injection barrier which was induced by the interface dipole formation between $C_{60}$ and Al. The mobility and $I_{ON}/I_{OFF}$ current ratio of OTFT with $C_{60}/Al$ electrode were 0.165 $cm^2/V{\cdot}s$ and $1.4{\times}10^4$ which were comparable with the normal Au electrode OTFT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.362-362
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• 2014

Atomic layer deposition (ALD) can be regarded as a special variation of the chemical vapor deposition method for reducing film thickness. ALD is based on sequential self-limiting reactions from the gas phase to produce thin films and over-layers in the nanometer scale with perfect conformality and process controllability. These characteristics make ALD an important film deposition technique for nanoelectronics. Tantalum pentoxide ($Ta_2O_5$) has a number of applications in optics and electronics due to its superior properties, such as thermal and chemical stability, high refractive index (>2.0), low absorption in near-UV to IR regions, and high-k. In particular, the dielectric constant of amorphous $Ta_2O_5$ is typically close to 25. Accordingly, $Ta_2O_5$ has been extensively studied in various electronics such as metal oxide semiconductor field-effect transistors (FET), organic FET, dynamic random access memories (RAM), resistance RAM, etc. In this experiment, the variations of chemical and interfacial state during the growth of $Ta_2O_5$ films on the Si substrate by ALD was investigated using in-situ synchrotron radiation photoemission spectroscopy. A newly synthesized liquid precursor $Ta(N^tBu)(dmamp)_2$ Me was used as the metal precursor, with Ar as a purging gas and $H_2O$ as the oxidant source. The core-level spectra of Si 2p, Ta 4f, and O 1s revealed that Ta suboxide and Si dioxide were formed at the initial stages of $Ta_2O_5$ growth. However, the Ta suboxide states almost disappeared as the ALD cycles progressed. Consequently, the $Ta^{5+}$ state, which corresponds with the stoichiometric $Ta_2O_5$, only appeared after 4.0 cycles. Additionally, tantalum silicide was not detected at the interfacial states between $Ta_2O_5$ and Si. The measured valence band offset value between $Ta_2O_5$ and the Si substrate was 3.08 eV after 2.5 cycles.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.348-348
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• 2014

차세대 디스플레이 구동 회로 소자를 위한 재료로서, Amorphous Oxide Semiconductor (AOS)가 주목받고 있다. AOS는 기존의 Amorphous Silicon과 비교하여 뛰어난 이동도를 가지고 있으며, 넓은 밴드 갭에 의한 투명한 광학적 특성을 가지고 있다. 이러한 장점을 이용하여, AOS 박막은 thin film transistor (TFT)의 active channel로 이용 되고 있다. 하지만, AOS를 이용한 TFT의 경우, 시간이 경과함에 따라 $O_2$ 및 $H_2O$ 흡착에 의해 전기적 특성이 변하는 현상이 있다. 이러한 현상은 소자의 신뢰성에 있어 중요한 문제가 된다. 이러한 문제를 연구하기 위해 본 논문에서는, AOS 박막을 이용하여 bottom 게이트형 TFT를 제작하였다. 이를 위해 먼저, p-type Si 위에 건식산화방식으로 $SiO_2$(100 nm)를 성장시켜 게이트 산화막으로 이용하였다. 그리고 Zn과 Sn이 1: 2의 조성비를 가진 ZnSnO (ZTO) 용액을 제조한 후, 게이트 산화막 위에 spin coating 하였다. Splin coating된 용액에 남아 있는 솔벤트를 제거하기 위해 10분 동안 $230^{\circ}C$로 열처리를 한 후, 포토리소그래피와 에칭 공정을 이용하여 ZTO active channel을 형성하였다. 그 후, 박막 내에 남아 있는 불순물을 제거하고 ZTO TFT의 전기적인 특성을 향상시키기 위하여, $600^{\circ}C$의 열처리를 30분 동안 진행 하여 junctionless형 TFT 제작을 완료 하였다. 제작된 소자의 시간 경과에 따른 열화를 확인하기 위하여, 대기 중에서 2시간마다 HP-4156B 장비를 이용하여 전기적인 특성을 확인 하였으며, 이러한 열화는 후처리 공정을 통하여 회복시킬 수 있었다. 열화의 회복을 위한 후처리 공정으로, 퍼니스를 이용한 고온에서의 열처리와 microwave를 이용하여 저온 처리를 이용하였다. 결과적으로, TFT는 소자가 제작된 이후, 시간에 경과함에 따라서 on/off ratio가 감소하여 열화되는 경향을 보여 주었다. 이러한 현상은, TFT 소자의 ZTO back-channel에 대기 중에 있는 $O_2$ 및 $H_2O$의 분자의 물리적인 흡착으로 인한 것으로 보인다. 그리고 추가적인 후처리 공정들에 통해서, 다시 on/off ratio가 회복 되는 현상을 확인 하였다. 이러한 추가적인 후처리 공정은, 열화된 소자에 퍼니스에 의한 고온에서의 장시간 열처리, microwave를 이용한 저온에서 장시간 열처리, 그리고 microwave를 이용한 저온에서의 단 시간 처리를 수행 하였으며, 모든 소자에서 성공적으로 열화 되었던 전기적 특성이 회복됨을 확인 할 수 있었다. 이러한 결과는, 저온임에도 불구하고, microwave를 이용함으로 인하여, 물리적으로 흡착된 $O_2$ 및 $H_2O$가 짧은 시간 안에 ZTO TFT의 back-channel로부터 탈착이 가능함과 동시에 소자의 특성을 회복 가능 함 의미한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.876-884
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• 2017

The current-voltage characteristics of Silicon(Si), Germanum(Ge), and hetero tunnel field-effect transistors(TFETs) with source-overlapped gate structure was investigated using TCAD simulations in terms of tunneling. A Si-TFET with gate oxide material $SiO_2$ showed the hump effects in which line and point tunneling appear simultaneously, but one with gate oxide material $HfO_2$ showed only the line tunneling due to decreasing threshold voltage and it shows better performance than one with gate oxide material $SiO_2$. Tunneling mechanism of Ge and hetero-TFETs with gate oxide material of both $SiO_2$ and $HfO_2$ are dominated by point tunneling, and showed higher leakage currents, and Si-TFET shows better performance than Ge and hetero-TFETs in terms of SS. These simulation results of Si, Ge, and hetero-TFETs with source-overlapped gate structure can give the guideline for optimal TFET structures with non-silicon channel materials.

• Journal of IKEEE
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• v.24 no.3
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• pp.859-866
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• 2020

This paper proposes a 2-ch DC-DC converter with a wide-input voltage range from 2.9V~5.6V for wearable AMOLED displays. For positive voltage V_POS, a boost converter is designed using an over-charged voltage permissible circuit (OPC) which generates a normal output voltage even if over-input voltage is applied, and a SPWM-PWM dual mode with 3-segmented power transistors to improve efficiency at light load. For negative voltage V_NEG, a 0.5x regulated inverting charge pump is designed to increase power efficiency. The proposed DC-DC converter was designed using a 0.18-㎛ BCDMOS process. Simulation results show that the proposed DC-DC converter generates V_POS voltages of 4.6 V and V_NEG voltage of -0.6V~-2.3V for input voltage of 2.9V to 5.6V. In addition, it has power efficiency of 49%~92%, output ripple voltage has less than 20 mV for load current range of 1 mA~70 mA.

• Journal of Sensor Science and Technology
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• v.7 no.1
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• pp.31-38
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• 1998

Multi-channel sensors can be used to increase the reliability and remove the random iloise in ion-sensitive field effect transistors(ISFETs). Multi-channel sensors is also an essential step toward potential fabrication of sensors for several ionic species in one device. However, when the multi-channel sensors are separately biased, the biasing problems become difficult, that is to say, the bias circuit is needed as many sensors. In this work, a circuit for biasing the four pH-ISFETs in null-balance method, where bias voltages are switched, was proposed. The proposed concept is need only one bias circuit for the four sensors. Therefore it has advantages of smaller size and lower power consumption than the case that all sensors are separately biased at a time. The proposed circuit was tested with discrete devices and its performance was investigated. In the recent trend, sensor systems are implemented as portable systems. So the verified measurement circuit was integrated by using the CMOS circuit. Fortunately, ISFET fabrication process can be compatible with CMOS process. Full circuit has a mask area of $660{\mu}m{\times}500{\mu}m$. In the future, this step will be used for developing the smart sensor system with ISFET.

• Journal of the Korean Vacuum Society
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• v.12 no.3
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• pp.168-173
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• 2003

Recently, according to the rapid progress in Flat-panel-display industry, there has been a growing interest in the poly-Si process. Compared with a-Si, poly-Si offers significantly high carrier mobility, so it has many advantages to high response rate in Thin Film Transistors (TFT's). We have investigated a new process for the high temperature Solid Phase Crystallization (SPC) of a-Si films without any damages on glass substrates using thin film heater. because the thin film heater annealing method is a very rapid thermal process, it has very low thermal budget compared to the conventional furnace annealing. therefore it has some characteristics such as selective area crystallization, high temperature annealing using glass substrates. A 500 $\AA$-thick a-Si film was crystallized by the heat transferred from the resistively heated thin film heaters through $SiO_2$ intermediate layer. a 1000 $\AA$-thick $TiSi_2$ thin film confined to have 15 $\textrm{mm}^{-1}$ length and various line width from 200 to 400 $\mu\textrm{m}$ was used as the thin film heater. By this method, we successfully crystallized 500 $\AA$-thick a-Si thin films at a high temperature estimated above $850^{\circ}C$ in a few seconds without any thermal deformation of g1ass substrates. These surprising results were due to the very small thermal budget of the thin film heaters and rapid thermal behavior such as fast heating and cooling. Moreover, we investigated the time dependency of the SPC of a-Si films by observing the crystallization phenomena at every 20 seconds during annealing process. We suggests the individual managements of nucleation and grain growth steps of poly-Si in SPC of a-Si with the precise control of annealing temperature. In conclusion, we show the SPC of a-Si by the thin film heaters and many advantages of the thin film heater annealing over other processes

• Journal of the Korean Vacuum Society
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• v.17 no.5
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• pp.435-441
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• 2008

In this paper, we investigated the electrical properties of triisopropylsilyl (TIPS) pentacene organic thin-film transistor (OTFT) depending on solvent type. We spin coated TIPS pentacene by using chlorobenzene, p-xylene, chloroform, and toluene as solvents. Fabricated OTFT with chlorobenzene shows field-effect mobility of $1.0{\times}10^{-2}cm^2/V{\cdot}s$, on/off ratio of $4.3{\times}10^3$ and threshold voltage of 5.5 V. In contrast, with chloroform, the mobility is $5.8{\times}10^{-7}cm^2/V{\cdot}s$, on/off ratio of $1.1{\times}10^2$ and threshold voltage of 1.7 V. Moreover we measured the grain size of each TIPS pentacene solvent by atomic force microscopy (AFM). From these results, it can be concluded that a solvent with higher boiling point results in better electrical characteristics due to large grain size and high crystallinity of TIPS pentacene layer. In this paper TIPS pentacene with chlorobenzene shows the best electrical properties.