• Journal of Advanced Navigation Technology
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• v.13 no.1
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• pp.48-53
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• 2009

The CMOS RF front-end for Global Positioning System(GPS)are implemented in 1P8M CMOS $0.13{\mu}m$ process. The LNAs consist of LNA1 with high gain and low NF, and LNA2 with low gain and high IIP3 for supporting operation with active and passive antenna. the measured performances of both LNAs are 16.4/13.8 dB gain, 1.4/1.68 dB NF, and -8/-4.4 dBm IIP3 with 3.2/2 mA form 1.2 V supply, respectively. The quadrature downconversion mixer is followed by transimpedance amplifier with gain controllability from 27.5 to 41 dB. The front-end performances in LNA1 mode are 39.8 dB conversion gain, 2.2 dB NF, and -33.4 dBm IIP3 with 6.6 mW power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.15-20
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• 2012

This paper presents a 5-Gb/s optical receiver circuit realized in a $0.13-{\mu}m$ CMOS technologies for the applications of high-speed digital interface. Exploiting modified RGC input stage at the front-end transimpedance amplifier, interleaving active feedback and source degeneration techniques at the limiting amplifier, the proposed optical receiver chip demonstrates the measured results of $72-dB{\Omega}$ transimpedance gain, 4.7-GHz bandwidth, and $400-mV_{pp}$differential output voltage swings up to the data rate of 5-Gb/s. Also, the chip dissipates 66mW in total from a single 1.2-V supply, and occupies the area of $1.6{\times}0.8mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.47-52
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• 2004

This paper presents a CMOS optical receiver design featuring wide input dynamic range and low bit error rate suitable for FTTH application. We achieved 60dB input dynamic range for up to 100Mbps by controlling the PMOS feedback resistance of transimpedance preamplifier according to its output signal level. Auto-bias circuit is designed in current mirror configuration to minimize duty error. Circuit simulation has been performed using 2-poly, 3-metal, 0.6um CMOS process parameters. The designed receiver consumes less than 130mW at 100Mbps with 5V power supply.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3124-3126
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• 2000

The application of IR(Infrared) communication is very wide and IR receiver has become a standard of home entertainment. A preamplifier with single 5V supply was designed for IR receiver IC. To operate at long distance, receiver IC should have high gain and low noise characteristic. To provide constant output signal magnitude, independent of transciever distance, gain limiting stage is needed. And to cut-off DC noise component effectively, large resistance and capacitance are required. Transimpedance type preamplifier, and diode limiting amplifier, and current limiting amplifier were designed. It is another function of current limiting amplifier that transforms single input signal to differential output signal. Using AMS BiCMOS model, both BJT version and MOS version was designed. Total power consumption is O.lmW, and IC size is $0.3mm^2$

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.31-39
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• 2011

In this paper, we propose a signal readout system with small area and low power consumption for CNT sensor arrays. The proposed system consists of signal readout circuitry, a digital controller, and UART I/O. The key components of the signal readout circuitry are 64 transimpedance amplifiers (TIA) and SAR-ADC with 11-bit resolution. The TIA adopts an active input current mirror (AICM) for voltage biasing and current amplification of a sensor. The proposed architecture can reduce area and power without sampling rate degradation because the 64 TIAs share a variable gain amplifier (VGA) which needs large area and high power due to resistive feedback. In addition, the SAR-ADC is designed for low power with modified algorithm where the operation of the lower bits can be skipped according to an input voltage level. The operation of ADC is controlled by a digital controller based on UART protocol. The data of ADC can be monitored on a computer terminal. The signal readout circuitry was designed with 0.13${\mu}m$ CMOS technology. It occupies the area of 0.173 $mm^2$ and consumes 77.06${\mu}W$ at the conversion rate of 640 samples/s. According to measurement, the linearity error is under 5.3% in the input sensing current range of 10nA - 10${\mu}A$. The UART I/O and the digital controller were designed with 0.18${\mu}m$ CMOS technology and their area is 0.251 $mm^2$.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1641-1644
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• 2005

현재의 인터넷과 같은 전자 통신망과 멀티미디어 시스템의 발달은 고속의 대용량 데이터 전송을 필요로 한다. 초고속 통신 시스템에서의 고속 데이터 전송은 주로 광섬유를 사용하는 광통신으로 이루어지고 있다. FTTH(Fiber To The Home)와 같은 광통신 시스템은 멀티미디어 커뮤니케이션을 위해 필요한 큰 데이터 전송률을 제공할 수 있기 때문에 더욱 더 중요성이 높아지고 있으며 이러한 광통신 시스템에서는 통신환경의 영향을 적게 받고 외부 조절이나 부품이 필요하지 않는 수신기 IC 의 개발이 요구되고 있다. 일반적으로 광통신 수신기에는 고속 동작에 적합한 특성을 가진 GaAs-MESFET 가 사용되고 있으나, 본 논문에서는 0.35um CMOS 2-poly 4-metal 공정을 이용하여 5Gbps 광수신기를 설계하였다. 설계된 수신기는 Preamplifier, Main amplifier, ABC 회로로 구성되어 있다. Transimpedance amplifier 형태의 Preamplifier 는 광검출기에 의해 생성된 전류 신호를 전압 신호로 변환한다. ABC 회로는 Peak_Hold 회로와 Bottom_Hold 회로로 구성되어 있다. 기존의 Peak_Hold 회로에서는 다이오드와 hold capacitor 를 이용하여 peak 값을 검출하도록 되어 있는데, 다이오드를 이용하는 경우 작은 입력 신호전압의 Peak 값을 검출하는 데 한계가 있다. 이러한 단점을 보완하고자 전류 거울형태의 Peak_Hold 회로를 설계하였다. 전류거울(current mirror)형태의 출력 신호의 duty error 를 줄이고 비트 에러율(Bit Error Rate)을 개선하는데 효과적이었다. 설계된 광수신기는 30dB 의 입력 dynamic range 와 입력 capacitance 3pF 에서 80MHz 의 대역폭을 가진다. 전력 소비량은 3.3V 전원 전압이 인가된 경우 약 150mW 정도이다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.421-422
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• 2008

In this paper, CMOS RF front-end circuits for an L1/L5 dual-band global positioning system (GPS)/Galileo receiver are designed in $0.13\;{\mu}m$ CMOS technology. The RF front-end circuits are composed of an RF single-to-differential low noise amplifier, an RF polyphase filter, two down-conversion mixers, two transimpedance amplifiers, a IF polyphase filter, four de-coupling capacitors. The CMOS RF front-end circuits provide gains of 43 dB and 44 dB, noise figures of 4 dB and 3 dB and consume 3.6 mW and 4.8 mW from 1.2 V supply voltage for L1 and L5, respectively.

• Journal of Sensor Science and Technology
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• v.21 no.3
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• pp.235-239
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• 2012

This paper presents frequency response compensation technique, and a self-oscillation circuit for capacitive microresonator with the compensation technique using programmable capacitor array, to compensate for the frequency response distorted by parasitic capacitances, and to obtain stable oscillation condition. The parasitic capacitances between the actuation input port and capacitive output port distort the frequency response of the microresonator. The distorted non-ideal frequency response can be compensated using two programmable capacitor arrays, which are connected between anti-phased actuation input port and capacitive output port. The simulation model includes the whole microresonator system, which consists of mechanical structure, transimpedance amplifier with automatic gain control, actuation driver and compensation circuit. The compensation operation and oscillation output of the system is verified with the simulation results.

• Journal of the Optical Society of Korea
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• v.20 no.3
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• pp.435-440
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• 2016

We developed a simple and real-time readout autocorrelator for several tens and sub-10fs pulses, based on the two photon absorption phenomena of a commercial GaP photodetector including a transimpedance amplifier. With a suitable gain adjustment, we demonstrated that the interferometric autocorrelation for sub-nJ pulses delivered as a high output voltage as to resolve all fringes in an autocorrelation trace with features of low noise and a low offset voltage. By fitting the measured quadratic power dependence of output voltages, we obtained the quantum efficiency of TPA for the GaP detector comparable with those of a GaAsP diode and an SHG with a thin BBO crystal. The autocorrelator of a TPA based GaP photodetector is highly suitable for sensitively measuring a few cycle pulses with a broad spectral distribution from 600 nm to 1100 nm.

• Journal of the Optical Society of Korea
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• v.20 no.5
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• pp.623-627
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• 2016

A power-adjustable fully-integrated CMOS optical receiver with multi-rate clock-and-data recovery circuit is presented in standard 65-nm CMOS technology. With supply voltage scaling, key features of the optical receiver such as bandwidth, power efficiency, and optical sensitivity can be automatically optimized according to the bit rates. The prototype receiver has −23.7 dBm to −15.4 dBm of optical sensitivity for 10⁻⁹ bit error rate with constant conversion gain around all target bit rates from 1.62Gbps to 8.1 Gbps. Power efficiency is less than 9.3 pJ/bit over all operating ranges.