• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.7
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• pp.501-508
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• 2004

In this paper, a coordinated scheduling algorithm is proposed to reduce end-to-end delay in distributed control of systems. For the algorithm, the analysis of practical end-to-end delay in the worst case is performed priory with considering implementation of the systems. The end-to-end delay is composed of the delay caused by multi-task scheduling of operating systems, the delay caused by network communications, and the delay caused by asynchronous timing between operating systems and network communications. Through some simulation tests based on CAN(Controller Area Network), the proposed worst case end-to-end delay analysis is validated. Through the simulation tests, it is also shown that a real-time distributed control system designed to existing worst case delay cannot guarantee end-to-end time constraints. With the analysis, a coordinated scheduling algorithm is proposed here. The coordinated scheduling algorithm is focused on the reduction of the delay caused by asynchronous timing between operating systems and network communications. Online deadline assignment strategy is proposed for the scheduling. The performance enhancement of the distributed control systems by the scheduling algorithm is shown through simulation tests.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.12-21
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• 2004

Error control is one of major concerns in many electronic systems. Experience shows that most malfunctions during system operation are caused by transient faults, which often mean abnormal signal delays that may result in violations of circuit element timing constraints. This paper presents a novel CMOS-based concurrent timing error detector that makes a flip-flop to sense and then signal whether its data has been potentially corrupted or not by a setup or hold timing violation. Designed circuit performs a quiescent supply current evaluation to determine timing violation from the input changes in relation to a clock edge. If the input is too close to the clock time, the resulting switching transient current in the detection circuit exceeds a reference threshold at the instant of the clock transition and an error is flagged. The circuit is designed with a $0.25{\mu}m$ standard CMOS technology at a 2.5 V supply voltage. The validity and effectiveness are verified through the HSPICE simulation. The simulation results in this paper shows that designed circuit can be used to detect setup and hold time violations effectively in clocked circuit element.

• ETRI Journal
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• v.32 no.6
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• pp.911-920
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• 2010

This paper presents a method of designing hybrid analog/asymmetrical square-root (SR) FIR filters. In addition to the conventional frequency domain constraints, the proposed method considers time-domain constraints as well, including the inter-symbol interference (ISI) and the opening of the eye pattern at the receiver output. This paper also reviews a systematic way to find the discrete-time equivalence of analog parts in a band-limited digital communication system. Thus, a phase equalizer can be easily realized to compensate for the nonlinear phase responses of the analog components. With the hybrid analog/SR FIR filter co-design, examples show that using the proposed method can result in a more robust ISI performance in the presence of the receiver clock jitter.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.519-522
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• 1998

The Constructive Battle simulation Model is very important to the recent military training for the substitution of the field training. However, real battlefield systems operate under rea-time conditions, they are inherently distributed, concurrent and dynamic. In order to reflect these properties by the computer-based simulation systems which represent real world processes, we have been developing constructive simulation model for several years. The constructive simulation system is one of the famous real-time system software, nd the one common feature of all real-time systems is defined as the correctness of the system depend not only on the logical result of computation, but also on the time at which the results are produced. Conventionally, scheduling and resource allocation activities which have timing constraints are major problem of real-time computing systems. To overcome these constraints, we elaborated on these issues and developed the simulation system on commercially available hardware and operating system with lock-free resource allocation scheme and rae monotonic scheduling.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2008.10a
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• pp.299-303
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• 2008

In this paper, we discuss the schedule problems for Korean Professional Baseball League (KPBL) and propose approaches to solve these problems by applying Integer Programming. A schedule in a sport league must satisfy lots of constraints on timing such as organizational, attractiveness, and fairness requirements. Organizational requirements cover a set of rules which have to guarantee that all the games can be scheduled according to the regulations imposed by Korean Baseball Organization (KBO). Attractiveness requirements focus on what stadium visitors, television spectators, and the clubs expect, that is, a varied, eventful, and exciting season. Fairness requirements have to guarantee that no team is handicapped or favored in comparison with the others. In addition to finding a feasible schedule that meets all the constraints, the problem addressed in this paper has the additional complexity of having the objective of minimizing the travel costs and every team has the balancing number of the games in home. We formalize the KPBL problem into an optimization problem and adopt the concept of evolution strategy to solve it. Using the method proposed, it is efficient to find better results than approaches developed before.

• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1646-1655
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• 1999

This thesis presents a new VHDL intermediate format CDDG(Control Dominated Data Graph) and a minimal constrained scheduling algorithm for an optimal control dominated ASIC design. CDDG is a control flow graph which represents conditional branches and loops efficiently. Also it represents data dependency and such constraints as hardware resource and timing. In the proposed scheduling algorithm, the constraints using the inclusion and overlap relation among subgraphs. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.

• Speech Sciences
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• v.10 no.3
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• pp.89-101
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• 2003

This paper investigates edge effects on the relationship between the underlying tonal sequence and its surface realization in the IP-final Accentual Phrase within the Optimality Theoretic framework. I will examine the way in which AP tones are aligned with their associated syllables in IP-final position. In Korean. Jun's (1996) 'see-saw effect' does not allow any two identical tones if they are marking a boundary of a prosodic group. A phonetic experiment conducted in this paper suggests that the 'see-saw effect' only apply to H boundary tones. Furthermore, it will be shown that the timing of tonal peaks is determined through the ranking of a set of violable constraints. The AP tonal realization is achieved through the access to the global intonation in a complicated way. In the course of discussion, pitch patterns in IP-medial Accentual Phrase will also be discussed.

• Journal of the Korean Society of Systems Engineering
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• v.13 no.1
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• pp.1-6
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• 2017

A stores management software which is embedded in the stores management system requires high-level reliability and real-time processing. It also required to implement and verify protocols which requires timing constraints to control various weapons. In this paper, we propose design methodology to design a stores management software and its support middleware based on the TMO (Time-triggered Message-triggered Object) model.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.247-249
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• 1988

The most space-consuming element of digital image processing system is the video memory. Though this problem is solved by DRAMs, timing constraints posed by video data rates. The cycle time of DRAMs can be diminished by serial transferring and reading or writing pixel datas at the same time. This paper resents the design of 1024${\times}$512 video memory using this technique.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.5
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• pp.387-397
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• 1991

This paper presents the design and implementation of a performance-driven logic synthesis system that automatically generates circuits satisfying the given timing and fanout constraints in minimal silicon area. After performing technology independent and dependent optimization, the system identifies and resynthesizes the gates with large loading delay due to excessive fanouts to eliminate the critical path. Experimental results for MCNC benchmark circuits show that proposed system generates the circuits with less delay by up to 20%.