• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.4
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• pp.37-42
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• 1984

In this paper, effective methods of symbol timing in a 9600 bps modem are presented. The symbol timing circuit consists of a square-low device followed by a high-Q narrow band-pass filter tuned to a symbol frequency. Also, the advantages of using a digital phase-tooted loop (DPLL) to suppress side tones are described, and statistical properties of timing wave are derived. In addition, the overall performances of the symbol timing circuit are verified by computer simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.206-219
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• 1996

This paper describes a data structure and evaluation algorithm to improve the perofmrances MOS logic-with-timing simulation in computation and accuracy. In order to efficiently simulate the logic and timing of driver-load networks, (1) a tree data structure to represent the mutual interconnection topology of switches and nodes in the driver-lod network, and (2) an algebraic modeling to efficiently deal with the new represetnation, (3) an evaluation algorithm to compute the linear resistive and capacitive behavior with the new modeling of driver-load networks are developed. The higher modeling presented here supports the structural and functional compatibility with the linear switch-level to simulate the logic-with-timing of digital MOS circuits at a mixed-level. This research attempts to integrate the new approach into the existing simulator RSIM, which yield a mixed-klevel logic-with-timing simulator MIXIM. The experimental results show that (1) MIXIM is a far superior to RSIM in computation speed and timing accuracy; and notably (2) th etiming simulation for driver-load netowrks produces the accuracy ranged within 17% with respect ot the analog simulator SPICE.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.3
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• pp.57-64
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• 2019

In this paper, an efficient prediction-based parallel simulation method using spatially partial simulation strategy is proposed for improving both the performance of the event-driven gate-level timing simulation and the debugging efficiency. The proposed method quickly generates the prediction data on-the-fly, but still accurately for the input values and output values of parallel event-driven local simulations by applying the strategy to the simulation at the higher abstraction level. For those six designs which had used for the performance evaluation of the proposed strategy, our method had shown about 3.7x improvement over the most general sequential event-driven gate-level timing simulation, 9.7x improvement over the commercial multi-core based parallel event-driven gate-level timing simulation, and 2.7x improvement over the best of previous prediction-based parallel simulation results, on average.

• Transactions of the Korean Society of Automotive Engineers
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• v.13 no.6
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• pp.48-55
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• 2005

In this paper, a mathematical model and a simulation method for the response time analysis of Local Interconnect Network(LIN) based network systems are proposed. Network-induced delays in a network based control system can vary widely according to the transmission time of message and the overhead time of transmission. Therefore, in order to design a distributed control system using LIN network, a method to predict and verify the timing behavior of LIN protocol is required at the network design phase. Furthermore, a simulation environment based on a timing model of LIN protocol is beneficial to predict the timing behavior of LIN. The model equation is formulated with six timing parameters deduced from timing properties of LIN specification. Additionally, LIN conformance test equations to verify LIN device driver are derived with timing constraints of the parameters. The proposed model equation and simulation method are validated with a result that is measured at real LIN based network system.

• Journal of Internet of Things and Convergence
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• v.1 no.1
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• pp.33-38
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• 2015

Hardware are developed in various architecture. It is necessary to verifying value of variables in modules generated in each clock cycles for timing simulation. In this paper, a test vector generator in software type generates test vectors for timing simulation of 224-bit ECDSA hardware modules in developing stage. It provides test vectors with GUI format and text file format.

• Transactions of the Korean Society of Automotive Engineers
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• v.4 no.3
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• pp.122-129
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• 1996

The spark timing is one of major parameters to the engine performance and emissions. The ECU controls the spark timing based on preset values, which are functions of load and speed, in most of today's automotive SI engine. In this system, the preset spark timing can be different from optimum value due to the deviations from mass production, aging effects and so on. In the present study, a control logic is investigated for real time adaptation of spark timing to optimal value. It has been found that crank angle of miximum cylinder pressure is one of the appropriate parameters to estimate the optimum spark timing throught experiment. It has also been observed for spark timing convergence by variation of engineering model factors. The simulation program including engineering model for cycle by cycle variation of combustion is developed for surveying spark timing control logic. It is also shown that simulation results reflect experiment outputs and reasonableness of spark timing control logic for crank angle of maximum cylinder pressure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.292-299
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• 2010

With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost issues of transistor-level simulations. Various techniques for fast SPICE simulations and Monte Carlo simulations are introduced. Moreover, process and aging variation issues are mentioned, along with promising methodologies.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.689-692
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• 2008

WAVE based on OFDM is made for vehicle to vehicle wireless communication. Its performance is decreased by continual timing delay in multipath fading channels after starting initial timing synchronization. In this paper, the tracking algorithm that synchronizes symbol timing is proposed to continually compensate additional timing delay. Computer simulation of the proposed algorithm is performed in the worst communication environment that applies to maximum timing delay. Computer simulation shows that the proposed algorithm can improve the system performance in various channel conditions.

• Transactions of the Korean Society of Automotive Engineers
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• v.16 no.5
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• pp.106-112
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• 2008

Modern vehicles require a high degree of refinement, including good drive ability to meet customer demands. Vehicle drive ability, which becomes a key decisive factor for marketability, is affected by many parameters such as engine control and the dynamic characteristics in drive lines. This paper focuses on the simulation of FTP-75 mode which is considered with spark timing control on transient condition. The acceleration is the most important factor for vehicle fuel economy. The retard of spark timing increases in proportion to acceleration. Likewise, bsfc(break specific fuel consumption) which is affected by spark timing also increases in proportion to acceleration. The result of simulation considered transient condition shows 0.3% of error comparing with a test on chassis-dynamometer.

• Journal of the Optical Society of Korea
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• v.13 no.3
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• pp.367-372
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• 2009

In this paper we propose an electronic domain timing phase selection scheme for the optical communication systems suffering from inter-symbol-interference (ISI) distortion due to chromatic dispersion (CD) or polarization mode dispersion (PMD). In the presence of CD/PMD a proper timing phase selection is important for discrete time domain equalizers, since different timing phases produce different nonlinear ISI channels of different severity. The proposed timing phase recovery scheme based on dispersion minimization (DM) practically approximates the optimal minimum mean squared error (MMSE) timing phase without training signals which reduces overall throughput substantially, especially in time-varying channels such as PMD. The simulation results show that the proposed DM timing agrees with MMSE timing phase, under proper normalization of the received signals, for various dispersion and OSNR.