• Transactions on Electrical and Electronic Materials
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• v.15 no.1
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• pp.37-40
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• 2014

A novel memory is reported, in which $Ge_2Sb_2Te_5$ (GST) has been used as a floating gate. The threshold voltage was shifted due to the phase transition of the GST layer, and the hysteretic behavior is opposite to that arising from charge trapping. Finite Element Modeling (FEM) was adapted, and a new simulation program was developed using c-interpreter, in order to analyze the small shift of threshold voltage. The results show that GST undergoes a partial phase transformation during the process of RESET or SET operation. A large $V_{TH}$ shift was observed when the thickness of the GST layer was scaled down from 50 nm to 25 nm. The novel 1 transistor PCM (1TPCM) can achieve a faster write time, maintaining a smaller cell size.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.7
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• pp.780-790
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• 1988

We have studied the hot-carrier-induced degradation caused by the high channel electric field due to the decrease of the gate length of MOSFET used in VLSI. Under DC stress, the condition in which maximum substrate current occures gave the worst degradation. Under AC dynamic stress, other conditions, the pulse shape and the falling rate, gave enormous effects on the degradation phenomena, especially at 77K. Threshold voltage, transconductance, channel conductance and gate current were measured and compared under various stress conditions. The threshold voltage was almost completely recovered by hot-injection stress as a reverse-stress. But, the transconductance was rapidly degraded under hot-hole injection and recovered by sequential hot-electron stress. The Si-SiO2 interface state density was analyzed by a charge pumping technique and the charge pumping current showed the same trend as the threshold voltage shift in degradation process.

• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.170-170
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• 2006

[ ${\pi}-conjugated$ ] organic and polymeric semiconductors are receiving considerable attention because of their suitability as an active layer for electronic devices. An organic inverter with a full swing and a high gain can be obtained through the good qualities of the transfer characteristics of organic thin-film transistors (OTFTs); for example, a low leakage current, a threshold voltage ($V_{th}$) close to 0 V, and a low sub-threshold swing. One of the most critical problems with traditional organic inverters is the high operating voltage, which is often greater than 20 V. The high operating voltage may result in not only high power consumption but also device instabilities such as hysteresis and a shift of $V_{th}$ during operation. In this paper, low-voltage and little-hysteresis pentacene OTFTs and inverters in conjunction with PEALD $Al_{2}O_{3}\;and\;ZrO_{2}$ as the gate dielectrics are demonstrated and the relationships between the transfer characteristics of OTFT and the voltage transfer characteristics (VTCs) of inverter are investigated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.25-32
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• 2011

We have analyzed adjacent cell dependency of threshold voltage shift caused by the cell to cell interference, and we proposed a 3-adjacent-cell model to model the pattern dependency of the threshold voltage shift. The proposed algorithm is verified by using MATLAB simulation and measurement results. In the experimental results, we found that accuracy of the proposed simple 3-adjacient-cell model is comparable to the widely used conventional 8-adjacient-cell model. The Bit Error Rate (BER) of LSB and of MSB is improved by 28.9% and 19.8%, respectively, by applying the proposed algorithm based on 3-adjacent-cell model to 20nm-class 2-bit MLC NAND flash memories.

• Journal of information and communication convergence engineering
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• v.14 no.1
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• pp.40-44
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• 2016

The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness T_ILD and dielectric constant ε_r of the inter-layer distance (ILD), the doping concentration N_d (N_a), and length L_g of the channel, and the side-wall length L_SW where the stacked FETs are coupled are studied. When N_d (N_a) < 10¹⁶ cm^-3 and L_SW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N_d (N_a) > 10¹⁶ cm^-3 or L_SW > 20 nm, the shift decreases and increases, respectively. M3INVs with T_ILD ≥ 50 nm and ε_r ≤ 3.9 can neglect the interaction between the stacked FETs, but when T_ILD or ε_r do not meet the above conditions, the interaction must be taken into consideration.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1226-1227
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• 2008

In this study, a single p-type Si nanowire - Au nanoparticles nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of p-type Si nanowire-based field effect transistor (FET) devices with Au nanoparticles embedded in the $Al_2O_3$ gate materials and without the Au nanoparticles. Drain current versus gate voltage ($I_{DS}-V_{GS}$) characteristics of a single p-type Si nanowire - Au nanoparticle NFGM device show counterclockwise hysteresis loops with the threshold voltage shift of ${\Delta}V_{th}$= 3.0 V. However, p-type Si nanowire based top-gate device without Au nanoparticles does not exhibit a threshold voltage shift. This behavior is ascribed to the presence of the Au nanoparticles, and is indicative of the trapping and emission of electrons in the Au nanoparticles.

• Journal of Electrical Engineering and Technology
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• v.2 no.2
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• pp.267-273
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• 2007

A depletion-mode MOSFET has been analyzed to evaluate its electrical behavior using a novel 3-D numerical simulation package. The characterizing analysis of the BC MOSFET was performed through short-channel narrow-channel and small-geometry effects that are investigated, in detail, in terms of the threshold voltage. The DIBL effect becomes significant for a short-channel device with a channel length of $<\;3({\mu}m)$. For narrow-channel devices the variation of the threshold voltage was sharp for $<4({\mu}m)$ due to the strong narrow-channel effect. In the case of small-geometry devices, the shift of the threshold voltage was less sensitive due to the combination of the DIBL and substrate bias effects, as compared with that observed from the short-channel and narrow-channel devices. The characterizing analysis of the narrow-channel and small-geometry devices, especially with channel width of $<\;4({\mu}m)$ and channel area of $<\;4{\times}4({\mu}m^2)$ respectively, can be accurately performed only from a 3-D numerical simulation due to their sharp variations in threshold voltages.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.212-214
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• 2005

The charge-pump circuit which is used to generate higher voltage than the available supply voltage has wide applications such as the flash memory of EEPROM Because the demand for high voltage comes from physical mechanism such as the oxide tunneling, the required pumped voltage cannot be scaled as the power supply voltage is scaled. Therefore, an efficient charge-pump circuit that can achieve high voltage from the available low supply voltage is essential. A new Analog Switch p-well CMOS charge pump circuit without the MOS device body effect is processed. By improve the structure of the circuit's transistors to reduce the threshold voltage shift of the devices, the threshold voltage of the device is kept constant. So, the circuit electrical characteristics are higher output voltage within a shorter time than the conventional charge pump. The propose analog switch CMOS charge pump shows compatible performance of the ideal diode or Dickson charge pump.

• Journal of Sensor Science and Technology
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• v.31 no.4
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• pp.271-277
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• 2022

We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the N_it distribution using TCAD simulation. As interface trap number density (N_it) increased, the threshold voltage increased while the drain current density decreased. Under N_it=5.0×10¹⁰ cm^-2 condition, the threshold voltage was 3.2 V for V_DS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the N_it distribution type, there was an increase in the subthreshold swing (SS) following an increase in N_it. Under U-shaped N_it distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Q_f) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

• Journal of Information Display
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• v.9 no.4
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• pp.35-38
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• 2008

This paper reports the electrical characteristics of polyvinylpyrrolidone (PVPy) and the performance of organic thin-film transistors (OTFTs) with PVPy as a gate insulator. PVPy shows a dielectric constant of about 3 and contributes to the upright growth of pentacene molecules with $15.3\AA$ interplanar spacing. OTFT with PVPy exhibited a field-effect mobility of 0.23 $cm^2$/Vs in the saturation regime and a threshold voltage of -12.7 V. It is notable that there was hardly any threshold voltage shift in the gate voltage sweep direction. Based on this reliable evidence, PVPy is proposed as a new gate insulator for reliable and high-performance OTFTs.