• Journal of Digital Convergence
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• v.11 no.11
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• pp.95-106
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• 2013

The Electronic Times, starting in 1982 as a weekly newspaper, has become an influential daily newspaper specializing in Information Technology(IT) since the mid 1990s in Korea. Particularly, it has shown significant and impressive financial achievements in the past thirty years since it was established. Also, it has contributed to the development in the field of IT journalism as well as the popularization of Information Technology. The primary purpose of this study is to provide useful lessons and implications to those who are interested in the evolution of The Electronic Times by investigating the financial performance of The Electronic Times and its contributions to the popularization of IT in our society.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.130-131
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• 2005

In the era of submicron devices, super ultra thin gate oxide characteristics are required. Titanium silicide process has studied gate oxide reliability and dielectric strength characteristics as the composition of gate electrode. In this study the author observed process characteristics on MOS structure. In view point of the process characteristics of MOS capacitor, the oxygen & Ti, Si2 was analyzed by SIMS analysis on before and after annealing with 1,2 step silicidation, the Ti contents[Count/sec]of $9.5{\times}1018$ & $6.5{\times}1018$ on before and after 2'nd anneal. The oxygen contents[Count/sec] of $4.3{\times}104$ & $3.65{\times}104$, the Si contents[Count/sec] of $4.2{\times}104$ & $3.7{\times}104$ on before and after 2'nd anneal. The rms value[A] was 4.98, & 4.03 on before and after 2'nd anneal.

• Journal of IKEEE
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• v.19 no.2
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• pp.271-275
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• 2015

This paper proposes a unified HEVC $4{\times}4$ IDCT/IDST architecture for area reduction. In general, $4{\times}4$ IDCT and $4{\times}4$ IDST blocks are implemented separately, and they are connected with multiplexers. In the proposed arechitecture, these two blocks are unified, and internal hardware resources such as multipliers are shared. This reduces the chip area. The synthesized block in 0.18 um technology is 2,795 gates, and the gate count is reduced by 9.44% in comparison with conventional designs.

• Journal of Sensor Science and Technology
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• v.10 no.2
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• pp.91-100
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• 2001

A $8{\times}8$ foveated (log-polar) retina chip for edge detection has been designed and fabricated using CMOS technology. Retina chip performs photo-input sensing, edge extraction and motion detection and we focused edge extraction. The pixel distribution follows the log-polar transform having more resolution in the center than in the periphery and can reduce image information selectively. This kind of structure has been already employed in simple image sensors for normal cameras, but never in edge detection retina chip. A scaling mechanism is needed due to the different pixel size from circumference to circumference. A mechanism for current scaling in this research is channel width scaling of MOS transistor. The designed chip has been fabricated using standard $1.5{\mu}m$ single-poly double-metal CMOS technology.

• Transactions on Electrical and Electronic Materials
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• v.9 no.1
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• pp.33-37
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• 2008

This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.389-397
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• 2007

This paper proposes miniaturized broadband parasitic patch antenna. The proposed antenna consists of a probe fed reduced size main patch and U-shaped parasitic patches. The parasitic patches are incorporated to the radiating edges of the main patch to miniaturize the antenna size. The broadband impedance matching can be achieved by either E-plane or H-plane electromagnetic coupling between main patch and parasitic elements. The size of radiating elements is $18{\times}17.6\;mm^2$ and the overall dimension of designed antenna with substrate and ground plane is $25{\times}30{\times}4\;mm^3$. The fabricated antenna on a FR4 substrate shows two resonant frequencies(5.12 GHz and 6.08 GHz) with 27.3 %(1.5 GHz) fractional bandwidth at 5.5 GHz center frequency. The calculated and measured radiation patterns are almost similar to conventional patch antenna.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.8
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• pp.718-729
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• 2015

A S / X dual broad band patch antenna with shared aperture structure is fabricated. A $2{\times}2$ perforated patch is used for S-band operation and a $2{\times}2$ patch antenna array is integrated in the $2{\times}2$ perforation for X-band operation. The measurement results of a S / X dual broad band patch antenna with shared aperture structure show the broad band characteristics larger than 20 % in both bands.

• Transactions on Electrical and Electronic Materials
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• v.12 no.5
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• pp.204-208
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• 2011

In this paper, the design area of a fabricated solar cell has been analyzed with respect to its charge density. The mathematical calculation used for charge-density derivation was obtained from the 2001 version of a MATHCAD program. The parameter range for the calculations was ${\pm}1{\times}10^{17}cm^{-3}$, which is in the normal parameter range for n-type doping impurities ($7.0{\times}10^{17}cm^{-3}$) and also for p-type impurities ($4.0{\times}10^{17}cm^{-3}$). Therefore, it can be said that the fabricated solar-cell design area has a direct effect on charge-density changes.

• Electrical & Electronic Materials
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• v.15 no.10
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• pp.17-22
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• 2002

• Proceedings of the Korean Magnestics Society Conference
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• 2003.12a
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• pp.163-163
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• 2003